Layout Engineer

Responsibilities

• Layout and verification of circuits to be used as part of state-of-the-art integrated circuits including:
• PLLs, Phase Interpolators
• High speed clock distribution networks
• Rx Decision-Feedback Equalizers and deserializers
• TX drivers and serializers
• High Speed DACs and ADCs
• This role involves:
• Developing detailed layout and performing all necessary verifications.
• Optimizing layout of circuits for power, performance, and integration to higher level IP / SOCs.
• Knowledge and Experience:
• The position requires extensive experience with layout of high-speed custom analog and digital circuits in area(s) like Serdes, HBM, UCIe and PLL.
• The candidate should be extremely familiar with the use of the Cadence Virtuoso tool suite to design and verify high-speed custom circuits, including Virtuoso schematic capture and layout. Innovus a plus.
• Design experience in advanced FinFET nodes is required.
• The ideal candidate will have wide-ranging experience, with a demonstrated ability to rely on both thorough understanding of layout fundamentals and creativity to solve circuit layout issues and problems.
• Education:
• BS degree in Electrical Engineering/related field and 8+ years of related years of experience or MS degree in Electrical Engineering/related field and 6+ years of related experience is strongly preferred
• Compensation and Benefits
• The annual base salary range for this position is USD 109,700.00 To USD 175,500.00
• If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Benefits

Additional Information

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Analog/Mixed Signal Layout Engineer This position is part of a highly skilled multi-geographical team tasked with the development of high speed analog, mixed-signal IPs covering HBM, UCIe, PLL, and many others areas using the latest 3nm and 2nm FinFET technology. The team will be developing key differentiating IPs used in the Artificial Intelligence, Machine Learning, High Performance Computing and Hyper-Scale Data Center markets. Each member of the team is expected to be committed to the team success, create new innovation, and ensure customer usage satisfaction with first time right quality mindset.

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Company Intel

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