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ASIC Design Engineer, BOOT and Power Management

External
NVIDIA logoNvidia · Bengaluru, India
Full-timeOn-siteToday
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Responsibilities

  • Own micro-architecture and RTL development of design modules
  • Micro-architect features to meet performance, power and area requirements
  • Work with HW architects to define critical features
  • Work with verification teams to verify the correctness of implemented features
  • Partner with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable.
  • What we need to see:
  • BTech/MTech with 2+ years of experience in crafting complex Units and CPU/micro-controller based Sub-systems
  • Knowledge of security standards, protocols and system security architectures of modern SOC's would be a significant plus
  • Excellent influencing skills resulting in collaboration with cross-cultural, multi geography and matrixed teams
  • Good debugging, analytical and problem solving skills
  • Great interpersonal skills and ability to work as an excellent teammate
  • #LI-Hybrid

Additional Information

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology-and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. We are now looking for RTL Design engineers for our BOOT and Power management Subsystem Design deployed in Automotive and Client chips. As one of the primary designers, you will be responsible for implementing system BOOT and overall power management architecture of next generation chips. One should possess strong digital design and verification fundamentals.


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