Senior ICE Emulation Design Engineer

Responsibilities

• Partition and synthesize large SOC RTL designs for emulation. Integrate internal and third-party IPs for emulation compatibility, and resolving timing, connectivity and other synthesis issues
• Setup and validate high-speed (e.g., PCIe, Ethernet, USB) and low-speed (e.g., I2C, SPI, UART) interfaces
• Configure host servers, boot environments to interact with the emulated design
• Integrate, develop and debug transactors, bridges and protocol adapters as needed
• Debug and root-cause embedded HW, SW and test failures in emulation
• Collaborate with RTL, DV and SW teams to resolve system level bugs
• Performance optimization
• BS or MS degrees or higher in EE, CE or related fields
• 7+ years of hands-on experience in prototyping, emulation, SOC design and validation
• Self-driven, good problem solving and communication skills
• Experience integrating and debugging high-speed and low-speed interfaces
• Familiarity with embedded software bring-up and bootloader/kernel interactions
• Proficiency with scripting languages (Python, Perl, TCL) for automation
• Preferred qualifications include: experience in design verification, hardware/software co-simulation, Linux device drivers, bare-metal FW or boot loaders
• Axiado is committed to attracting, developing, and retaining the highest caliber talent in a diverse and multifaceted environment. We are headquartered in the heart of Silicon Valley, with access to the world's leading research, technology and talent.

Additional Information

The Senior Emulation Design Engineer position is your opportunity to join one of the industry's leading companies in platform security management and ransomware detection for cloud datacenters, 5G infrastructure and disaggregated compute ecosystems. You will be responsible for converting large, complex SOC designs, including third-party IPs, into emulation-ready environments, enabling system level validation and debugging, software development and performance analysis. This role is critical for validating the interoperability of our design with commercial AI servers, and for bridging the gap between hardware and software, as well as supporting SW development.

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Company Intel

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