Virtual Platform Hardware Modeling Engineer

Responsibilities

• Design and develop SystemC TLM models to accurately represent the SoC architecture integrating emulated processors, DSPs, Network-on-Chip, DMA and memory controllers, etc...
• Integrate first-party and vendor models into the Virtual Platform, develop automated workflows to ensure register-level accuracy and complete connectivity at the SoC level, minimizing manual intervention and enabling continuous integration.
• Collaborate with silicon architects, digital designers and verification engineers to design and develop high-fidelity, fast C++ models for first-party IP.
• Coordinate virtual platforms with hardware development programs, validating multiple SoCs and architectural changes with system software and firmware engineering, enabling end-to-end silicon validation test frameworks.
• Enhance the virtual platforms to enable SoC and system architecture exploration by instrumenting models for power and performance metrics, allowing for data-driven design decisions and trade-off analysis to optimize system performance and power consumption.

Requirements

• B.S. degree in Computer Science or Electrical Engineering or equivalent experience.
• 2+ years experience in hardware model simulation, virtual platform, performance modeling of complex SoCs or high-fidelity hardware accelerators.
• High proficiency in modern C++ in the domains of chip-design, electronic design automation or simulation.
• General familiarity with SoC components: embedded processors such as ARM A/M series, Risc-V, DSP, DMA, Cache Hierarchy, DRAM, Network-on-chip, AMBA protocols. Extensive experience in at least one of these areas.
• Experience with modern buildframeworks and continuous integration systems, such as CMake, Bazel and CI frameworks such as Jenkins, GitLab CI/CD.
• Experience with debugging and profiling tools, such as GDB or other debuggers
• Experience with the SystemC/TLM library
• Experience with virtual platform development tools and frameworks, such as Synopsys Virtualizer, Cadence Virtual Platform, Imperas OVP, or ARM Fast Models
• Familiarity with processor/DSP architectures, such as ARM, RISC-V, and XTensa
• Familiarity with NoC, MMU, address translations, and cache modeling
• Familiarity with the standard C++ concurrency support library: threads, atomic operations, memory ordering, etc...
• Proficiency in Python to automate design flows, creation of collateral data
• Experience with high level C/C++ synthesis (HLS)
• Working knowledge of Verilog
• California Pay Range
• $70 - $75 USD

Benefits

Additional Information

We are seeking a modeling Engineer to develop high-level models of complex SoC hardware. The virtual platforms combine models of custom hardware accelerators for vision, 2D and 3D graphics, machine learning and more, within a multi-core, multi-level memory hierarchy SoC architecture, and serve as the primary simulation vehicle for system software and firmware. The ideal candidate will be proficient in hardware simulation using C++, and understand the firmware development processes.

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Company Intel

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