Senior Layout Engineer

Responsibilities

• Own chip layout end-to-end, including top-level floorplan and RF block layout, ensuring clean GDS and all required collateral for manufacturing release (40%).
• Lead RF layout of critical blocks, working closely with design engineers to implement optimised circuits that meet timing, performance, and reliability targets (20%).
• Coordinate and guide the layout team, including remote contributors, setting priorities, providing technical direction, and tracking delivery against schedule (15%).
• Interface with Marketing, Applications, Test, Validation, and Reliability teams to finalise and distribute chip-level floorplans and die footprints (10%).
• Collaborate with EDA teams on foundry PDK management and drive continuous improvement in layout performance and efficiency (10%).
• Perform other relevant tasks as assigned (5%).

Requirements

• Bachelor's degree in Electrical, Electronics, or Communication Engineering.
• 8+ years' experience in analog layout design, including 3+ years at high-frequency (10 GHz+).
• Deep understanding of CMOS/BiCMOS analog layout practices, parasitics, electromigration, IR drop, device matching, ESD, and latch-up.
• Expert proficiency in layout development and verification tools, including Cadence Virtuoso and Mentor Graphics Calibre (LVS/DRC/PEX).
• Proven track record of delivering chip-level layout and owning the tape-out process.
• Demonstrated leadership in task delegation, team coordination, and project tracking.
• Experience in high-speed IC layout at frequencies of 25 GHz and above.
• Proficiency in automation scripting (SKILL, Python, Perl, Shell) to enhance layout efficiency.
• Expertise in layout and optimisation of high-frequency passive components such as T-coils and inductors.
• Foundational understanding of common IC circuit topologies.
• Strong structured thinking, attention to detail, and effective communication skills.
• Career Growth Philosophy:
• At Semtech, we believe that innovation starts with people. We are committed to empowering professional development through mentorship, continuous learning resources, and a collaborative, idea-rich engineering environment.
• Additional Notes:
• The intent of this job description is to describe the major duties and responsibilities performed by incumbents of this job. Incumbents may be required to perform job-related tasks other than those specifically included in this description.
• All duties and responsibilities are essential job.

Benefits

Additional Information

Location: Stansted, UK Our Team: Semtech's High-Speed IC Design team is a group of highly skilled engineers dedicated to developing next-generation analog ICs for datacentres, 5G wireless networks, and fibre-to-the-home applications. We leverage deep expertise in transimpedance amplifiers (TIAs) and laser drivers (LDs) to deliver innovative solutions that power global communication infrastructure. Job Summary: The Senior Analog Layout Engineer is responsible for the end-to-end layout of high-speed ICs, including transimpedance amplifiers and laser drivers, from initial floorplan through to tape-out. This role involves leadership of the layout team, close collaboration with design engineers, and ensuring delivery of high-performance, manufacturable IC designs that meet project objectives.

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