Staff RTL Design Engineer - PCIe

Requirements

• Master's/Bachelor's degree in Electronics/electrical Engineering with 4 + years of relevant experience in RTL design
• Experience on end‑to‑end PCIe/CXL subsystem RTL design execution and sign‑off
• Proven experience delivering complex PCIe/CXL IP or subsystems from architecture through RTL closure
• Strong hands‑on experience in SystemVerilog / Verilog RTL development
• Expertise in PCIe protocol architecture including link, transaction, and PHY interaction layers
• Strong understanding of CXL.io, CXL.cache, and CXL.mem architectures
• Deep knowledge of ARM‑based SoC integration and AMBA protocols (AXI‑4, CHI, ACE)
• Experience designing high‑performance, low‑latency data paths and handling ordering, coherency, and error mechanisms
• Solid grasp of C locking, Resets, CDC/RDC, low‑power techniques, and performance optimization
• Experience supporting lint, CDC/RDC, synthesis, and design sign‑off flows
• Proficient in debugging functional and performance issues at subsystem and SoC levels
• Experience using industry‑standard EDA tools from Synopsys, Cadence, Mentor/Siemens
• Proficient in scripting languages such as Tcl / Perl / Python
• Experience with version control systems such as GIT, SVN, etc.
• Additional Compensation and Benefit Elements
• All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
• Interview Integrity
• To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
• #LI-CP1

Additional Information

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell Data Centre Engineering (DCE) - Compute & Storage (CCS) BU has been at the forefront of developing and delivering leading-edge, high performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast‐growing product lines, Marvell Technology is powering the next‐generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Automotive Compute market segments. The team focusses on the Custom ASIC business, Cloud AI solutions & Enterprise/Career solutions including the CXL product line What You Can Expect Own and drive PCIe/CXL subsystem micro architecture definition , RTL implementation, and integration Collaborate closely with Architecture teams to translate requirements into robust RTL designs Work with Design Verification teams on test‑plan reviews, debug, and coverage closure Partner with Physical Design and DFT teams to ensure PD‑friendly and DFT‑ready RTL Support silicon bring‑up and post‑silicon debug , working with firmware and validation teams Drive design quality improvements, coding best practices, and reuse across projects Participate in design reviews, milestone reviews, and cross‑functional technical discussions Mentor junior designers and provide technical leadership within the PCIe/CXL design domain

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