Lead CAD & Design Enablement Engineer

About the role

We are seeking a CAD Engineering Lead to support a fast-paced silicon engineering organization spanning both digital and analog design disciplines. This role is responsible for maintaining and improving the EDA environment, enabling efficient design workflows, developing automation solutions, and serving as a key technical partner to engineering teams throughout the chip development lifecycle.

Responsibilities

• Serve as the primary point of contact for day-to-day CAD, EDA, and design environment support for digital and analog engineering teams.
• Maintain, enhance, and troubleshoot design, verification, implementation, analog, and signoff flows across the silicon development lifecycle.
• Develop, deploy, and maintain automation, scripting, and infrastructure solutions that improve engineering productivity, design quality, and execution efficiency.
• Diagnose and resolve EDA tool, licensing, environment, and workflow issues to minimize engineering downtime and accelerate project execution.
• Partner closely with digital design, verification, physical design, analog, and systems engineering teams to understand requirements, address challenges, and continuously improve design methodologies.
• Evaluate, qualify, and deploy new EDA tool releases, methodologies, and best practices to improve team effectiveness and design quality.
• Work directly with EDA vendors to investigate technical issues, drive issue resolution, and influence future tool capabilities and enhancements.
• Partner with IT, infrastructure, and operations teams to develop and maintain a reliable, scalable, and high-performance computing environment that supports demanding EDA workloads.
• Monitor, analyze, and optimize compute, storage, network, and licensing resources to maximize engineering productivity, improve resource utilization, and reduce infrastructure bottlenecks.
• Collaborate with IT teams on infrastructure planning, capacity forecasting, deployment of new technologies, and resolution of system-level issues impacting design and verification workflows.
• Create and maintain documentation, training materials, and support processes that enable efficient onboarding and effective use of design tools and methodologies.
• Coordinate and manage external CAD contractors and service providers, including task definition, prioritization, technical oversight, deliverable review, and quality assurance.
• Lead and coordinate a blended team of internal and external CAD resources to execute CAD roadmap initiatives, methodology improvements, and engineering support activities.
• Define and drive continuous improvement initiatives for CAD methodologies, automation frameworks, infrastructure, and engineering workflows to support organizational growth and future silicon programs.
• Contribute to long-term CAD strategy and roadmap planning, balancing immediate engineering support needs with scalable infrastructure and methodology investments.

Requirements

• 5+ years of experience supporting semiconductor design teams in a CAD, EDA, design methodology, or silicon infrastructure role.
• Strong understanding of digital and/or analog IC design flows, including design entry, simulation, verification, implementation, and signoff methodologies.
• Hands-on experience administering and supporting industry-standard EDA tools from vendors such as Cadence, Synopsys, Siemens EDA (Mentor), or Ansys. Proficiency in scripting and automation using Python, Tcl, Shell, Perl, or similar languages.
• Experience developing and maintaining engineering workflows, automation frameworks, and productivity-enhancing tools. Strong knowledge of Linux/Unix operating systems and distributed compute environments.
• Experience with EDA license management, job scheduling systems, and compute infrastructure used for semiconductor development.
• Understanding of compute, storage, networking, and infrastructure considerations for large-scale design and verification workloads.
• Experience troubleshooting complex technical issues spanning EDA tools, design flows, infrastructure, and user environments.
• Ability to partner effectively with cross-functional engineering teams, including digital design, verification, physical design, analog, systems, and software engineers.
• Experience working with IT and infrastructu

Additional Information

About OLIX AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten-year-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode. Rack-scale co-design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance.

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Company Intel

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