Senior Staff Engineer, Digital IC Design

Requirements

• Master's degree and/or PhD in EE, CS or related fields and 6+ years of experience.
• Good personal communication skills and team working spirit.
• Hardworking and motivated to be part of a highly competent design team.
• Must have good post-RTL experience including synthesis, timing analysis and physical design. Able to perform custom placement and routing for mixed-signal designs. Flexible to move between all post-RTL design activities as required. Good understanding of block and top-level physical timing closure.
• Must be proficient in the following skills:
• Logic or physical synthesis using Synopsys or Cadence tools
• DFT generation and verification
• Static timing analysis using Primetime
• Physical design for 28nm and beyond
• Strong Perl and Tcl scripting skill
• Highly desirable skills:
• Low power design
• Circuit level or custom design experience
• Floorplanning, clock-tree synthesis and power planning/analysis
• Signal integrity and physical verification
• Additional Compensation and Benefit Elements
• All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
• Interview Integrity
• To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
• #LI-SYU

Benefits

Additional Information

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products. What You Can Expect ASIC design engineer responsible for post-RTL design flow. He/She will be responsible for block and/or chip level synthesis, timing closure, DFT generation, and ECOs. The responsibilities include but are not limited to. - Improve the design methodology and flow. - Synthesis, timing closure, and DFT support for various types of SerDes IPs ranging from 10Gbps to 224Gbps data rates for different applications. - Collaborate with Analog/Digital design teams to deliver competitive SerDes IP solutions for all the Marvell product lines. - Provide support to the product teams, for both pre and post-silicon

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