ASIC Design Engineer

Responsibilities

• Contribute to the architecture and micro-architecture of high-performance ASIC subsystems for next-generation data center silicon.
• Design and implement high-frequency, high-performance RTL in Verilog / System Verilog, meeting aggressive timing, power, and area targets.
• Develop design and micro-architecture specifications and participate in technical design reviews.
• Collaborate closely with verification teams to resolve design issues and drive functional coverage closure.
• Work with physical design teams to address timing, synthesis, and place-and-route challenges.
• Debug and root-cause issues across simulation, system integration, and silicon bring-up environments.
• Contribute to post-silicon validation and lab bring-up to ensure successful silicon delivery.

Requirements

• Bachelors + 7 years of related experience, or Masters + 4 years of related experience, or PhD + 1 year of related experience.
• Experience with at least one full ASIC tapeout, preferably at advanced technology nodes.
• Strong expertise in Verilog/System Verilog RTL design for high-performance ASICs.
• Understanding of timing closure, power optimization, and clock gating techniques.
• Experience with ASIC design flows including simulation, synthesis, and static timing analysis.
• Experience with debug and problem-solving skills.
• Experience with data center networking or storage architectures, including RDMA and NVMe-over-TCP.
• Experience with ARM-based SoC architectures and protocols such as AXI, CHI, APB, and AHB.
• Design experience with high-speed interfaces including PCIe, Ethernet MAC, DDR/LPDDR, and DMA engines.
• Experience integrating third-party IPs into SoC designs.
• Proficiency in engineering scripting and automation (Python, Perl, TCL, shell).
• Experience with emulation, prototyping, or formal verification tools.
• Why Cisco?
• We are Cisco, and our power starts with you.
• Message to applicants applying to work in the U.S. and/or Canada:
• The starting salary range posted for this position is $165,000.00 to $241,400.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
• U.S. employees are eligible for paid time away as described below, subject to Cisco's policies:
• 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt em

Benefits

Additional Information

The application window is expected to close on: 07/10/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . This role requires being onsite in San Jose, CA at least 4 days/week. Meet the Team The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco's core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms-like Silicon One-are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development-from design to qualification to production-is within our team, we're able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

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