Director, Physical Design & CAD Methodology (ASIC/SoC)

Responsibilities

• Define the global physical design methodology strategy across all phases: synthesis, floor planning, placement, clock tree synthesis (CTS), routing, timing closure, and physical verification.
• Architect and deploy advanced CAD flows to support complex, high-performance System-on-Chip (SoC) and Application-Specific Integrated Circuit (ASIC) designs.
• Drive innovation in hierarchical design, multi-die/chiplet integration, and 2.5D/3D IC Design methodologies.
• Manage, mentor, and grow a high-performing team of CAD and physical design methodology engineers.
• Allocate engineering resources efficiently to support concurrent, multi-project execution timelines.
• Develop a culture of continuous learning, automation, and technical excellence.
• Serve as the primary technical liaison with major EDA vendors (e.g., Synopsys, Cadence, Siemens).
• Evaluate, benchmark, and select state-of-the-art EDA tools to improve engineering productivity and design quality.
• Negotiate tool licensing requirements, influence vendor product roadmaps, and manage the CAD budget.
• Drive the creation of robust scripting infrastructure (using Tcl, Python, Perl) to automate repetitive tasks and ensure flow consistency.
• Explore and integrate AI/ML-driven EDA features to optimize PPA and shorten turnaround times.
• Partner closely with RTL Design, DFT (Design for Test), Architecture, and Physical Implementation teams to ensure seamless handoffs and tool interoperability.
• Collaborate with external foundries to integrate Process Design Kits (PDKs) and resolve complex deep sub-micron physical effects (e.g., electromigration, IR drop, thermal management).

Requirements

• Master's or Ph.D. degree in Electrical Engineering, Computer Engineering, or a highly related technical field with 10+ years of experience in ASIC/SoC physical design and CAD methodology.
• 5+ years of experience in a formal leadership or people management role
• Experience navigating the complexities of advanced process geometries (7nm, 5nm, 3nm and 2nm)
• Experience with full RTL-to-GDSII design flows
• Experience with physical verification (DRC, LVS, ERC), Static Timing Analysis (STA), sign-off processes, and power integrity (IR drop and electromigration)
• Proficiency in EDA tool suites (e.g., Innovus, Fusion Compiler, PrimeTime, Calibre
• Why Cisco?
• We are Cisco, and our power starts with you.
• Message to applicants applying to work in the U.S. and/or Canada:
• The starting salary range posted for this position is $230,100.00 to $325,300.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
• U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cis

Benefits

Additional Information

The application window is expected to close on: 06/29/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . Meet the Team The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco's core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms-like Silicon One-are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development-from design to qualification to production-is within our team, we're able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

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