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Silicon Design-for-Test (DFT) Engineer

External
matx logoMatx · Mountain View, CA
$120K–$275K/yrFull-timeOn-site1mo ago
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Requirements

  • Hands-on experience with DFT implementation - MBIST, at-speed scan and scan compression.
  • Strong knowledge of modern DFT standards and protocols: JTAG (IEEE 1149.1), IJTAG (IEEE 1687), and Streaming Scan Networks (SSN) .
  • Experience or Working Knowledge of loading and validating PHY firmware via serial interfaces (SPI, I2C, or JTAG), including understanding of bootloader sequences and register map initialization.
  • Solid experience integrating PHY DFT interfaces (e.g., SERDES PHY test modes, analog test buses into the SoC DFT architecture.
  • Experience with system-level DFT access - hierarchical test access, test data compression, and multi-die/chiplet DFT - is a strong plus.
  • Familiarity with EDA tools such as Synopsys DFT Compiler, Mentor Tessent, or equivalent.

Benefits

The US base salary for this full-time position is determined based on a variety of factors including role, experience, location, job related skills, and relevant education and training. Career length is only a guideline for compensation.Early Career - $120,000 - $275,000 + equityMid Career - $175,000 - $450,000 + equitySenior Career - $275,000 - $600,000 + equityA Stake in our success A cash/equity mix that fits your needs and option to do early exerciseHealth & Wellness Company subsidized Health, Dental, Vision, and Life insurance; Pre-tax Health Savings Accounts with generous company contribution (even if you don't)Time To Recharge 4 weeks paid time off (accrued), 12 company holidays, and 3 weeks remote/flexible work per yearSupport to Parents Up to 12 weeks of paid parental leave, regardless of your path to parenthoodLearning & Development $1,500 yearly towards your professional development e.g. conferences, courses, and other learning opportunitiesTeam Connection Team Lunches, quarterly off-sites, and regular town hallsFinancial Wellbeing 401K and/or Roth IRA, with 5% company contribution, even if you don't!Flexible Spending Accounts Pre-tax spend accounts for medical, dental/vision, dependent care, parking, and transit expensesCommute On Us For those commuting up to 1 hour, put your rideshare cost on our company card and reclaim the drive-time to get work done!MatX E[x]tras $50 per month to use on the perks you care about mostRemote Perks We work remotely Monday & Friday, supported by home-tech setup, and remote wifi expense reimbursementAll candidates must be authorized to work in the United States and work from our offices in Mountain View Tuesdays-Thursdays.This position requires access to information that is subject to U.S. export controls. This offer of employment is contingent upon the applicant's capacity to perform job functions in compliaHealth insuranceDental insuranceVision insurance401(k)Remote work optionsFlexible scheduleEquity / stock optionsParental leave

Additional Information

What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking a Silicon Design-For-Test (DFT) engineer to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The successful candidate for this role will be responsible for implementation of DFT functions for performant and functionally accurate silicon for MatX products across compute, memory management, high-speed connectivity and other key technologies in leading-edge process nodes. What You'll Do Here Design and develop functional test solutions for SERDES PHY , covering loopback, eye diagram characterization, and margin testing. Perform DFT integration of PHY IP blocks, including boundary scan, BIST interfaces, and test mode control signals, and develop robust pattern porting flows from IP-level to SoC-level. Develop and maintain firmware loading flows for PHY bring-up and test - including SPI/JTAG-based firmware download, register initialization sequences, and debug support during test program development. Collaborate closely with verification, firmware, and test engineering teams to develop and bring up silicon test programs from simulation to ATE. Execute DFT implementation and verification flows for block-level DFT insertion , including scan chain closure, ATPG pattern generation, and sign-off. Support test escapes root cause analysis and drive continuous improvement of DFT coverage and test quality.

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