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RTL Design Engineer

External
etched logoEtched · San Jose
$150K–$275K/yrFull-timeOn-site12mo ago
Machine LearningPythonTransformers
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Benefits

Medical, dental, and vision packages with generous premium coverage$500 per month credit for waiving medical benefitsHousing subsidy of $2k per month for those living within walking distance of the officeRelocation support for those moving to San Jose (Santana Row)Various wellness benefits covering fitness, mental health, and moreDaily lunch + dinner in our officeUnlimited compute budget subject to ROI justificationHow we're different:We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.Health insuranceDental insuranceVision insurance

Additional Information

About Etched Etched is building the world's first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips operate correctly and efficiently. You will develop and implement design verification strategies for both our existing and upcoming ASIC designs. In this role, you will work closely with state-of-the-art architectures for machine learning. You do not need to have experience working with these yet, but you will be willing and able to learn quickly. You will work in a fast-paced environment with a high degree of autonomy, and be responsible for a key part of Etched's success. Representative projects Implement a block to efficiently compute floating point math operators Provide feedback to the uArch team to make sure blocks meet timing and area constraints You may be a good fit if you At least 5 years of work experience in RTL development. Experience with high-speed digital logic. Proficiency in standard RTL design and synthesis tools Familiarity with verification work and writing test benches Are able to learn quickly about transformers and other aspects of modern artificial intelligence Willing to start quickly Strong candidates may also have experience with (Nice-to-have qualifications) Experience with PCIe, Ethernet, or HBM technologies Familiarity with transformer models and machine learning. Familiarity with numerical representations and functions Ability to program with Python or another scripting language We encourage you to apply even if you do not believe you meet every single qualification.


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