Senior Technologist, Mask Design Engineering ((Extensive IC Layout Design-22 years of expertise in custom/AMS across analog, digital, and mixed-signal domain)

Responsibilities

• Advanced Layout Design & Optimization
• Lead the development, optimization, and integration of peripheral and core circuit layouts across Analog, Digital, and Mixed‑Signal domains. Ensure adherence to design specifications, performance targets, and foundry rules while driving correct‑by‑construction methodologies.
• Design Verification & Sign‑off Leadership
• Oversee DRC, LVS, parasitic extraction, and sign‑off flows. Ensure design integrity, manufacturability, and first‑pass silicon success through rigorous verification and closure strategies.
• Power Distribution & Floor planning Architecture
• Architect full‑chip power distribution networks and floorplans to optimize electrical performance, minimize parasitic's , and reduce die size. Provide guidance on placement, routing, and hierarchical layout planning.
• Cross‑Functional Technical Leadership
• Methodology Development & Continuous Improvement
• Define and enhance layout methodologies, automation flows, and best practices to improve productivity, consistency, and design quality. Champion innovation in layout automation and process optimization.
• Technical Mentorship & Review
• Provide technical direction to senior layout engineers, conduct critical block reviews, and elevate team capability through mentorship and knowledge sharing.
• Your Experience and Role Expectation
• Extensive IC Layout Expertise : 22+ years of full‑chip custom layout experience across analog, digital, and mixed‑signal designs with deep knowledge of power routing, signal planning, and physical constraints.
• Tool & Verification : Expert in DRC/LVS, parasitic extraction, EM/IR analysis, and sign‑off verification using industry‑standard tools.
• 'Floor planning Strength : Proven ability to architect efficient floorplans, optimize placement, and reduce die area using correct‑by‑construction approaches.
• Cross‑Site Leadership : Strong track record collaborating with multi‑site, cross‑disciplinary teams and leading small technical groups to successful design convergence.
• Communication & Methodology : Excellent communication skills with a proactive approach to methodology development, automation, and continuous improvement.

Additional Information

Role: Mask Design Senior Technologist (Principal Engineer) Role Overview As a VLSI Layout Technologist, you will serve as a senior technical member driving full‑chip and block‑level layout architecture across Analog, Digital, and Mixed‑signal domains. Expectation is to influence design strategy, lead complex layout development, and ensure first‑pass silicon success.

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Company Intel

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