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Senior Principal Test Engineer

External
Marvell logoMarvell · Irvine, CA
Full-timeOn-siteToday
GitJavaLeadershipPython
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Requirements

  • Core Qualifications & Technical Expertise
  • 15+ years of Test Engineer experience with focus on New Product Introduction (NPI), developing and releasing ATE test solutions enabling High Volume Manufacturing (HVM) ramp
  • Proven leadership experience with 5+ years leading teams and driving test development initiatives
  • Strong knowledge and hands-on experience in PMIC (Power Management IC) testing
  • Proven collaboration with firmware teams to develop and implement ATE firmware solutions
  • Experience utilizing pattern translation tools to convert DFT (Design-for-Test) patterns into ATE-compatible test formats
  • Solid understanding of ATE hardware design processes and key components.
  • In-depth knowledge of Advantest V93000 (93K) hardware and software platforms
  • Advanced programming skills in Java, C/C++, and Python within ATE environments
  • Strong understanding of communication protocols, including debugging and validation
  • Well versed in the use of subversion control such as SVN or Git for test program development and released.
  • Bonus Qualifications
  • Experience with IVR (Integrated Voltage Regulator) and photonic products , including testing methodologies and application knowledge.
  • Solid understanding of RF/microwave principles , including signal integrity and the impact of mechanical factors on performance.
  • Expert-level experience (preferred) with automated test platforms such as: Advantest V93000 (SmarTest 8) and Teradyne UltraFLEX (IG-XL)
  • Hands-on experience with thermal characterization and testing , including an understanding of thermal effects on device performance.
  • Expected Base Pay Range (USD)
  • 162,000 - 239,760, $ per annum
  • The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
  • Additional Compensation and Benefit Elements
  • All qualified applicants will receive consideration

Benefits

Health insuranceEquity / stock optionsPerformance bonus

Additional Information

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell is seeking a highly talented Senior Principal Test Engineer to lead New Product Introduction (NPI) of Marvell Packaged Integrated Voltage Regulator (PIVR) powering next-generation high-performance computing (HPC) chipsets. The individual is charged to work with cross functional teams to develop electrical testing of Marvell's PIVR products, designing test hardware with thermal and mechanical considerations. In doing so, establishes standardized processes and methodologies that can be leveraged across Operations Engineering Team. Idea candidate should have hardware knowledge including load board and socket design for High Power Products. Ability to collaborate with internal teams and partners in developing new hardware. Knowledgeable and experience dissecting any proposed hardware solution. Solid understand and hands-on experience developing test solution for Integrated Voltage Regulator (IVR) or Power Management Integrated IC (PMIC) on state of the art ATE Test Systems. What You Can Expect Test Lead - Pre-Silicon & Post-Silicon Validation Lead test program development in coordination with Program Management (PGM) and post-silicon teams, aligning key milestones to support successful New Product Introduction (NPI) deployment. Responsible for overseeing all aspects of test development across both pre-silicon and post-silicon phases. Collaborate with cross-functional teams to define and develop comprehensive test plans. Drive ATE hardware design , including design initiation, review, and approval prior to manufacturing sign-off. Develop and implement test solutions for Integrated Voltage Regulator (IVR) and Packaged Integrated Voltage Regulator (PIVR) including production test program and test hardware.


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