NPI Engineering Intern

Responsibilities

• Conduct a structured review of academic journals and conference publications related to advanced CMOS devices
• Analyze how channel material properties (e.g., band structure, strain, surface roughness, scattering mechanisms) impact:
• Carrier mobility
• Drive current and leakage
• Device reliability
• Study the role of interfacial layers (IL) as thickness scales to sub ‑ nanometer regimes, including:
• Material quality and defect characteristics
• Trade ‑ offs between scaling, performance, and long ‑ term stability
• Evaluate the impact of High ‑ k Metal Gate (HKMG) stacks , including:
• High ‑ k dielectric and metal gate material choices
• Gate leakage behavior and threshold voltage (Vt) tuning
• Dipole formation, oxygen vacancy effects, and process variability
• Integrate findings across channel, IL, and HKMG to describe cross ‑ layer interaction effects on device performance
• Organize and document findings in a clear, structured, and reusable format for technical discussion
• Deliverables
• A comprehensive written report describing how channel materials, IL properties, and HKMG stacks influence electrical performance and reliability in advanced CMOS devices
• A summary presentation suitable for technical reviews
• A curated and organized database of analyzed literature
• What You Will Gain
• Hands ‑ on experience analyzing state ‑ of ‑ the ‑ art and beyond ‑ CMOS device technologies
• Deep exposure to device physics and gate stack engineering challenges at advanced technology nodes
• Experience in translating academic research into insights relevant for industrial R&D
• Close interaction with experienced engineers and researchers in advanced device and materials development

Requirements

• Currently pursuing a PhD degree in:
• Electrical Engineering
• Materials Science
• Applied Physics
• Solid ‑ State or Semiconductor ‑ related disciplines
• Strong foundation in semiconductor physics and device engineering
• Ability to read, analyze, and synthesize complex technical literature
• Strong written communication skills in English
• What sets you apart
• Background in CMOS device physics , gate stack engineering, or reliability
• Familiarity with concepts such as mobility degradation, interface traps, high ‑ k dielectrics, or metal gate work function engineering
• Prior research experience in device, materials, or process technology
• Apply today to be part of what's next.
• To learn more about ASM, find us at asm.com and on LinkedIn , Facebook , Instagram, X and YouTube .

Additional Information

Step into a career with ASM, where cutting edge technology meets collaborative culture. For over 55 years ASM has been ahead of what's next, at the forefront of innovation and what's technologically possible. With more than 4,500 ASMers representing 70 nationalities, our people and our advanced semiconductor devices are playing a crucial role in trends such as 5G, cloud computing, AI, and autonomous driving. But we're more than just a tech company. We value diversity, inclusion and sustainability as we strive to make a positive impact on the world. Our development programs help support your growth, shaping your future and pushing the boundaries of innovation to unleash potential. Job's mission We are seeking a highly motivated Engineering Intern to support research and analysis of advanced CMOS transistor electrical behavior , with a focus on how channel materials, interfacial layers (IL), and High ‑ k Metal Gate (HKMG) stacks influence device performance and reliability. This internship centers on deep technical literature review and knowledge synthesis . The intern will analyze published research to understand the physical mechanisms and material-device interactions that govern electrical characteristics in advanced logic devices. The results will be consolidated into a structured knowledge base to support ongoing and future device and process development activities. This role is well suited for PhD students with strong backgrounds in semiconductor physics, device engineering, or materials science who are interested in advanced device architectures and gate stack engineering.

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