Staff System Software Engineer, RTL-to-GDS Flow Platform

Responsibilities

• Build and modernize production RTL-to-GDS flow infrastructure across synthesis, place-and-route, timing, signoff, ECO, and handoff workflows
• Extend YAML/configuration systems to model workflow intent, stage contracts, validation markers, generated artifacts, override order, and backward-compatible project behavior
• Improve Make, Perl, Tcl, Python, and related launch infrastructure for generated runsets, EDA tool setup, distributed execution, status tracking, and failure diagnosis
• Build faster prelaunch and in-run checks for missing inputs, stale generated files, invalid hooks, broken environment setup, bad constraints, and inconsistent design state
• Develop job-control and observability capabilities for hierarchical and internally launched workflows, including parent-child job attachment, logs, provenance, and structured status
• Partner with design and CAD users to debug failures across EDA tools, Linux environments, shared filesystems, schedulers, generated collateral, and configuration layers
• What We Need To See:
• B.S. or M.S. in CS, EE, CE, or equivalent experience
• 12+ years building, modernizing, or operating production EDA, VLSI CAD, RTL-to-GDS, physical design, or large engineering workflow systems
• Strong hands-on experience with RTL-to-GDS or implementation flows, including setup, generated collateral, tool launch, checks, timing/signoff handoff, and debug workflows
• Strong Tcl and Make experience in real EDA automation environments, plus practical software engineering skill in Python, Perl, Go, or C++
• Ability to reason about layered configuration, includes, overrides, variable expansion, generated outputs, validation state, and compatibility with older projects
• Excellent Linux debugging fundamentals and a track record of improving legacy production systems without breaking active users
• Ways To Stand Out From The Crowd:
• Background with production flows using commercial synthesis, place-and-route, timing, extraction, DRC/LVS, power, or signoff tools
• Experience designing workflow engines, runset generators, configuration systems, template-driven automation, or job-control infrastructure
• Background with distributed schedulers and shared compute environments such as LSF, Slurm, Grid Engine, or similar systems
• Experience with NFS-heavy shared filesystems, stale state, partial writes, generated input files, provenance tracking, and reproducibility issues
• Experience building structured checks, validation markers, data-fidelity tracking, dependency tracing, observability, or better-tested legacy Tcl/Make/Perl replacements
• Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 184,000 USD - 287,500 USD for Level 4, and 224,000 USD - 356,500 USD for Level 5. You will also be eligible for equity and benefits .
• Applications for this job will be accepted at least until May 26, 2026. This posting is for an existing vacancy.
• NVIDIA uses AI tools in its recruiting processes.

Additional Information

The VLSI Productivity and Infrastructure team supports 1000+ chip design engineers with strong automation and workflows necessary to create world-changing silicon. We are building the next generation of production semiconductor design-flow infrastructure: a control-plane-driven RTL-to-GDS platform that turns design intent, configuration, generated collateral, EDA tool execution, distributed jobs, validation checks, and shared project state into observable, repeatable implementation workflows. This role is for a senior flow/platform engineer who can work across synthesis, physical design, timing, signoff, ECO, and hierarchical execution. If you can envision and evolve legacy Tcl/Make/Perl/YAML infrastructure into a cleaner, more structured system while keeping active projects running, this role is for you!

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Company Intel

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