Memory Design Automation - Memory modeling

About the role

The MediaTek's Memory modelling team collaborates with the world-wide memory design teams to create and qualify front-end models for use in the ASIC design flow. Team members will also be expected to perform circuit design verification to ensure memory circuits robustness. What you do: Develop and integrate automation code into existing memory compilers to generate models meant for ASIC design flow. Develop automation flow and scripts with Perl or Python. Execute EDA tools from vendors such as Synopsys, Mentor to verify models' correctness. Stay up to date with current modeling standards and development to improve models and flows for better memory IP performance. Work with memory design, compiler team and DFT team and tool vendors to resolve model issues and find solutions. What you bring: Must have a Bachelor's degree or higher in Electrical Engineering, Electronics Engineering, or related Experience in Linux systems will be a plus. Good understanding of verilog syntax and its various aspects, such as behavioral, RTL and synthesizable verilog is a must. Good understanding of liberty timing syntax. Good understanding of upf and system verilog. Knowledge and experience with EDA simulation tools such as VCS, NC is required Experience with EDA tools will be helpful: -DFT: Logicvision, Tessent, Fastscan -Synthesis: Design compiler, Genus -Simulation tools:VCS, QuestaSim, NC -STA tools such as PrimeTime Good scripting and flow automation skills, in Perl or Python. A team player, meticulous, able to work and learn independently are important attributes for this job. Location: One North, Singapore

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Company Intel

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