Design Verification Engineer

Responsibilities

• Develop and maintain SystemVerilog/UVM verification environments for SerDes and PHY blocks
• Write testbenches, functional coverage models, and assertions
• Run simulations, analyze failures, and debug both RTL and testbench issues
• Collaborate with design, architecture, and analog teams on block-level and top-level verification
• About Altera

Requirements

• BSc in Electrical Engineering, Computer Engineering, or equivalent
• 0-5 years of experience in digital design or verification (internships, academic projects, or industry)
• Working knowledge of SystemVerilog and basic familiarity with UVM concepts
• Solid digital design fundamentals: synchronous logic, FSMs, pipelining, clock domain crossing
• Strong analytical and debug mindset - you enjoy getting to the bottom of a problem
• Good communication skills in English (spoken and written)
• Job Type:
• Regular
• Shift:
• Shift 1 (Romania)
• Primary Location:
• Bucharest, Romania (Remote)
• Additional Locations:
• Posting Statement:

Benefits

Additional Information

Job Details: Job Description: We're looking for a talented, self-motivated engineer to join our Design Verification team. We work on some of the most technically challenging silicon in the industry, spanning digital and analog design, DSP pipelines, and firmware-hardware co-verification. This role is ideal for an early-career engineer who wants to build deep technical expertise in high-speed silicon verification. You'll work alongside experienced engineers on real silicon shipping to production, with plenty of opportunity to learn, grow, and take ownership as you ramp up. What We Build Our team develops and verifies high-speed SerDes IP - the physical layer technology that moves data at speeds from 10Gbps to 100Gbps+ across PCIe, Ethernet, and other industry-standard interfaces. Getting this right matters: the world's data moves through what we build.

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