Digital IC Design Engineer - Early Career

Requirements

• Bachelor's degree in Computer Science, Electrical Engineering or related fields and 1-3 years of related professional experience OR Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields.
• If currently in school, must graduate no later than December 2026.
• Solid understanding of computer architecture Knowledge in micro-architecture design, RTL coding, and functional verification
• Proficient using Verilog/VHDL Knowledge of design and verification tools
• Experience in Perl/Python/Tcl is a plus
• Must have effective interpersonal, teamwork, and communication skills
• Demonstrates good analysis and problem-solving skills
• Has an inherent sense of urgency and accountability
• Must have the ability to multi-task in a fast paced environment
• Expected Base Pay Range (USD)
• 108,500 - 160,510, $ per annum
• The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
• Additional Compensation and Benefit Elements
• All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
• Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com .
• Interview Integrity
• To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
• #LI-RM1

Benefits

Additional Information

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Data Center Engineering organization designs, builds, and integrates the processor, coherent cache, interconnect fabric, and the IO-bridge. The team works across Architecture, RTL, Verification, Physical Design disciplines to deliver high-performance, low-power SoCs for use in the cloud / data center and networking equipment including servers, switches, routers, secure gateways, firewall, network monitoring, and smartNICs. What You Can Expect Contribute by developing the next generation of cloud, networking, and security processors Work with Architects and Verification Engineers to develop complex, high performance and timing critical designs Be responsible for block level micro-architecture design and RTL coding Provide area/power optimization and design trade-offs Block and chip level synthesis, timing closure and formal verification Support chip bring-up and validation teams

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