IP Design Verification Engineer

Requirements

• Minimum qualifications are required to be initially considered for this position.
• Relevant Work experience include: IP or SoC verification experience using System Verilog/UVM
• Reading and interpreting technical specs and Register Transfer Level (RTL) code for debug
• Implementation of verification environments that include use of constrained-random stimulus
• Code/Functional Coverage analysis
• Writing System Verilog Assertions (SVA)
• Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
• Mixed-Signal Verification
• Experience with UCIe or PCIe or I/O
• Job Type:
• Experienced Hire
• Shift:
• Shift 1 (United States of America)
• Primary Location:
• US, California, Santa Clara
• Additional Locations:
• US, Oregon, Hillsboro
• Business group:
• Posting Statement:
• Position of Trust
• N/A

Benefits

Additional Information

Job Details: Job Description: The world is transforming - and so is Intel. Here at Intel, we believe the world needs technology that can enrich the lives of every person on earth. We work every single day to design and manufacture silicon products that empower people's lives. Do you love to solve technical challenges? Do you enjoy working with cross functional teams to deliver solutions for products ? If so, come join us to do something wonderful. As an IP Verification Engineer, you will be working on UCIe Mixed-Signal IP delivering to multiple Server SoCs. A successful candidate will have proven experience demonstrating the following skills and behavioral traits: Analytical and problem-solving skills Verbal/written communication skills Effective team player with continuous learning mindset Willingness to balance multiple tasks Willingness to work in a fast-paced environment and have as much fun and growth as possible in the process The primary responsibilities for this role will include, but are not limited to: Test bench development, directed/constrained random test generation in UVM Closely working with design team to review specifications and architecture, define verification plan, coverage, and improve methodology Run RTL and gate level functional verification, debug failures, and analyze coverage Support mixed-signal verification using Verilog models of analog IP

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Company Intel

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