Design Verification Software Intern

Responsibilities

• Build software and scripts for high performance simulation and emulation of CPUs
• Improve verilog for optimal simulation performance and fpga emulation synthesis
• Maintain and enhance the Git infrastructure to support CI/CD, nightly regressions across multiple development platforms
• Build software tools and scripts for design flow automation
• Experience & Qualifications:
• Currently working towards a Bachelors program
• Strong programming skills. C++, Python, SystemVerilog preferred.
• Solid experience with the Linux operating system
• Experience with version control. Git preferred.
• Interest in CPUs, hardware design, and/or programming
• Willing to learn and adapt
• Compensation for all interns at Tenstorrent ranges from $50/hr - $70/hr including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
• Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Additional Information

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. This role entails design and development of scalable infrastructure and software for the verification of high performance CPUs going into industry leading AI/ML architecture. The successful candidate will be responsible for development and automation of many aspects of the verification environment. The person coming into this role will have opportunities such as: writing low-level RISC-V assembly, building complex low-latency multithreaded testbenches, database programming, software testing and release automation, verilog coding and optimization of CPU components, and contributing to open source projects in the RISC-V ecosystem. This role is on site, based out of Santa Clara, CA or Austin, TX. This is for our Fall 2026 Semester

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