(Sr.) Staff Engineer, Digital IC Design

Requirements

• Master's degree and/or PhD in EE, CS or related fields and 3+ years of experience.
• Good personal communication skills and team working spirit.
• Hardworking and motivated to be part of a highly competent design team.
• Must be proficient in the following skills:
• Fundamental concepts in digital logic design
• Understand ASIC verification flows and methodologies
• Verilog and SystemVerilog/SystemC/Vera
• Strong Perl and Tcl scripting
• UNIX Shell scripting (Csh, Bash)
• Highly desirable skills:
• Formal verification
• Low power design
• MATLAB and C/C++ based system simulation and evaluation
• DSP function hardware implementation knowledge
• Additional Compensation and Benefit Elements
• All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
• Interview Integrity
• To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
• #LI-SYU

Additional Information

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell Central Engineering (CE) develops Marvell's most advanced High-Speed SerDes (HSS) IPs covering multiple applications, Switch, Automotive, Storage, Optics, etc. Acting as the engine to the company, Central Engineering provides the source of power to every business unit in Marvell system. Central System Engineering (CSE) in Central Engineering, independent of other CE functions including DSP algorithm development, circuit design, physical design, packaging, etc., is a function team responsible of validating all Marvell HSS IPs in the lab environment and supporting all Marvell business units for fast and smooth SoC production. Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products. What You Can Expect ASIC design engineer responsible for the design, verification and evaluation of digital circuits in high-speed data communication ICs. The candidate will be involved in verification plan development, test environment setup, modeling, testcase development and execution. He/She will be responsible for block and/or chip level verification. The responsibilities include but not limited to. Improve the design methodology and flow. Design and verification for various types of SerDes IPs ranging from 10Gbps to 224Gbps data-rates for different applications. Collaborate with Analog/DSP/Digital Design/FW/AE teams to deliver the competitive SerDes IP solutions for all the Marvell product lines. Provide the support to the product teams, for both pre and post silicon Test chip integration

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