FPGA IP Software Development Engineer

Responsibilities

• RTL Architecture & Coding : Define micro-architecture and implement clean, efficient, and reusable RTL code using System Verilog , Verilog , or VHDL .
• IP Integration & Flow Management : Drive the full FPGA tool flow including synthesis, place-and-route (P&R), constraints creation, and static timing analysis (STA).
• Timing Closure : Resolve complex multi-clock designs, Clock Domain Crossing (CDC) anomalies, and timing violations to ensure robust operation.
• Verification & Simulation : Develop testbenches and run block-level behavioral simulations to thoroughly debug and validate logic functionality before target implementation.
• Hardware Bring-up & Debug : Validate RTL functionality on actual evaluation boards using lab equipment like logic analyzers, oscilloscopes, and protocol compliance testers.
• Cross-functional Collaboration : Collaborate with software and board-level hardware teams to establish specifications, interface architectures, and system integration paths.
• Required Qualifications & Technical Skills
• Education : Bachelor's or master's degree in Electronics Engineering, Electrical Engineering, VLSI, Embedded Systems, or a closely related technical discipline.
• Hardware Description : 7+ years of dedicated experience writing production-grade RTL using System Verilog, Verilog, or VHDL .
• Toolchain Expertise : Hands-on proficiency with major FPGA vendor suites like Altera Quartus Prime , AMD / Xilinx Vivado or Microchip Libero .
• Analysis & Linting : Strong familiarity with static verification methodologies including Linting, CDC validation, and constraint troubleshooting.
• Scripting Skills : Ability to automate tool workflows using Tcl, Python, or Shell scripting .
• Preferred / Bonus Skills
• Familiarity with embedded SoC architectures (e.g., ARM Cortex, RISC-V) and hardware-software co-design.

Requirements

• Job Type:
• Regular
• Shift:
• Shift 1 (India)
• Primary Location:
• Bengaluru, Karnataka, India
• Additional Locations:
• Posting Statement:

Benefits

Additional Information

Job Details: Job Description: We are seeking a highly skilled and motivated RTL Design Engineer to drive the architecture, development, and implementation of our Soft IP solutions. In this role, you will own the end-to-end FPGA Soft IP development lifecycle-from micro-architecture definition and RTL coding to timing closure, simulation, and physical hardware validation. You will work closely with embedded software, hardware, and systems engineering teams to deliver robust, high-performance FPGA Soft IP solution solutions.

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Company Intel

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