RTL Design Lead
External
Erbity Private · Noida, IndiaPrepare for this interview
EliteAI-generated questions, company research, and talking points tailored to this role
About the role
Job Description: Lead RTL design activities for complex ASIC/SoC development projects. Work closely with architecture and verification teams to define micro-architecture and implementation strategies. Develop high-quality RTL using Verilog/SystemVerilog. Drive block-level design, integration, lint, CDC, and synthesis activities. Ensure design quality and timely project execution. Debug and resolve design issues during simulation, synthesis, and silicon bring-up stages. Collaborate with cross-functional teams including DFT, Physical Design, and Verification. Mentor junior engineers and support technical reviews. Required Skills: Strong experience in RTL Design for ASIC/SoC projects. Hands-on expertise in Verilog/SystemVerilog. Good understanding of AMBA protocols (AXI/AHB/APB). Experience with synthesis, lint, CDC, and low-power design methodologies. Strong debugging and problem-solving skills. Prior team handling or technical leadership experience is preferred.
Your Match
How well this role fits your profile.
Company Intel
What employees say
Worked at Erbity Private Limited? Share your experience