Senior Staff RTL Design Engineer

Requirements

• To be successful in this role, you must:
• Bachelor's degree in Computer Science, Electrical Engineering or related fields and 8-12 years of related professional experience.
• Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.
• Experience in Micro-architecture for complex Custom SoC/ASIC products.
• Excellent Logic design and debug skills.
• RTL design experience, Synthesis, static-timing closure, formal verification, gate-level simulations and block-level function verification.
• Design knowledge of one/more industry-standard bus protocols (AXI, AHB, APB) a plus.
• Hands-on experience for all aspects of chip-development process with proficiency in front-end design tools and methodologies is a must.
• Knowledge of scripting languages, such as Python
• Experience with highspeed, low power, and area optimized designs.
• Experience working with multi-clock designs, DFT, resets, LEC, Lint, etc.
• Expected Base Pay Range (USD)
• 135,900 - 201,130, $ per annum
• The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
• Additional Compensation and Benefit Elements

Benefits

Additional Information

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell Custom Solutions partners with the world's most advanced technology companies-including leading hyperscalers, cloud data center operators, and telecom providers-to architect and deliver next-generation custom silicon that powers AI infrastructure, cloud computing, and 5G networks. Our team drives innovation at the forefront of semiconductor design, working on cutting-edge System-on-Chips (SoCs) built in the most advanced process nodes (3nm, 2nm) that leverage best-in-class IP portfolios spanning high-speed SerDes (112G+), advanced die-to-die interconnects, custom HBM memory architectures, PCIe Gen 6/7, and CXL 3.0 technologies-all integrated using breakthrough advanced packaging techniques including 2.5D, 3D, and co-packaged optics. In Custom Solutions, you'll collaborate with elite engineering teams across disciplines-from architecture and design through validation and production-to solve complex technical challenges that directly impact how billions of people experience technology, ensuring that every design meets the exacting specifications and performance requirements that our customers depend on to power their mission-critical infrastructure. What You Can Expect The Senior Staff SoC Design Engineer role focuses on SoC microarchitecture, RTL design, and full-chip integration for high-performance designs. The position involves implementing and integrating complex IP across subsystems, ensuring correct functionality while meeting performance, power, and area (PPA) targets at the SoC level. Responsibilities span the full front-end design flow - from architecture and specification through RTL development, integration, and design sign-off - in close collaboration with verification, physical design, and architecture teams. Define microarchitecture and develop Verilog/SystemVerilog RTL for SoC-level components, including interconnects, memory interfaces, and global logic such as reset, clocking, and power management. Collaborate with verification teams to review test plans, support functional debug, and help close coverage gaps during development. Run standard design checks such as lint and CDC/RDC, define timing constraints, and work with synthesis and physical design teams to ensure the design meets implementation requirements. Coordinate with IP teams to integrate complex interfaces and resolve subsystem-level issues. Contribute to design methodology, improve integration workflows, and provide technical guidance to other engineers.

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