Staff Engineer, Digital ASIC Design (CONTRACT)

Requirements

• Baseline skills/experiences/attributes:
• BS/MS/PhD in EE/CE (or equivalent practical silicon design experience).
• 8+ years (typical Staff level) in digital IC / ASIC / SoC design with substantial hands-on RTL ownership and at least one major-IP or full-chip tapeout cycle.
• Proven ownership of a defined digital IP/subsystem from micro-architecture and RTL implementation through verification closure and tapeout support.
• Strong RTL skills in SystemVerilog/Verilog, including pipelined datapaths, control logic/state machines, and high-throughput streaming interfaces.
• Experience designing sustained high-throughput datapaths, including buffering/FIFOs, arbitration/backpressure, bandwidth budgeting, and SRAM/memory interface considerations.
• Strong understanding of silicon-level design constraints, including clock/reset architecture, CDC/RDC risk mitigation, power-aware design, and PPA tradeoffs.
• Effective collaboration with verification to drive functional closure through signoff (SV/UVM and/or Python-based frameworks such as cocotb).
• Experience building and using bit-accurate reference models (e.g., Python) to validate fixed-point behavior and enable end-to-end checking.
• Experience supporting post-silicon bring-up/debug and silicon correlation, partnering with firmware/validation to root-cause issues and deliver fixes.
• Strong cross-functional communication to close hardware-firmware interfaces (register maps, control/status paths, data-plane contracts) with systems/firmware stakeholders.
• Ideally, you also have these skills/experiences/attributes (but it's ok if you don't!):
• Experience implementing compute-intensive DSP pipelines (e.g., beamforming, filtering, noise reduction, MAC-heavy datapaths) with fixed-point design discipline.
• Exposure to ultrasound / medical imaging systems or sensor data acquisition pipelines and image-quality KPIs.
• Advanced-node experience (28nm or smaller), including timing sensitivity and third-party IP integration.
• (Optional, only if this matches the role) Experience integrating programmable compute subsystems (MPU/accelerator), including control interfaces and memory/bandwidth tradeoffs.
• Values
• Innovation is what we do. Our values are how we make it happen. Butterflies are and believe in...
• Patient-Centric Innovators: Our mission is THE mission.
• Empowered to Impact: Every voice matters.
• One Team, One Goal: Unity fuels progress.
• Growth Champions: We embrace challenges.
• Action-Oriented Achievers: We follow through, every time.
• Location
• This is a hybrid position and will be based out of our office in either the Greater SF Bay Area or Burlington, MA.
• For this temporary role, we are only considering candidates who are legally authorized to work in the United States and who do not now or in the future require sponsorship or transfer for employment visa status.
• Butterfly network does not accept agency resumes for this temporary position.

Benefits

Additional Information

Job Description The role of the Staff Digital ASIC Designer offers the opportunity to work within the heart of the product development team and founders and to own the core of what will set Butterfly Network apart. This individual will design, implement, and verify digital signal processing, high speed interface, and system-on-a-chip logic for a suite of next-generation products. As part of our team, your core responsibilities will be: Develop low-power RTL for large SoCs in an advanced node. Implement and optimize signal processing algorithms in RTL. Integrate multiple embedded processor cores into a large design. Develop efficient high bandwidth on chip data paths. Other Technology, Architecture, & Productivity duties as assigned

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