Senior CAD Manager - RTL-to-GDS Methodology & Infrastructure, Annapurna Labs

Requirements

• Bachelor's degree in electrical engineering, computer engineering, or equivalent
• 15+ years of experience in semiconductor CAD/EDA, methodology, or physical design
• 5+ years of experience in people management or technical leadership of engineering teams
• Experience taking SoCs through tape-out at advanced nodes (7 nm or below) using industry-standard digital implementation flows
• Experience with RTL-to-GDS toolchains including synthesis, place-and-route, static timing analysis, parasitic extraction, power/IR analysis, and physical verification
• Experience with low-power design flows (UPF/CPF), MMMC corners, and POCV/SSTA at advanced nodes
• Experience with scripting and automation (Tcl, Python, or Perl) and version control systems (Git or Perforce)
• Experience scaling CAD compute infrastructure (LSF, Slurm, or equivalent) and managing license capacity at scale
• Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related field
• Experience with AI/ML-driven flow automation or ML features in EDA tools (e.g., predictive QoR/runtime models)
• Experience with package- and system-aware flows (2.5D/3D IC, chiplets, UCIe) and SI/PI co-design
• Experience with cloud-based EDA workflows and hybrid on-prem/cloud compute strategy
• Experience with formal verification, RTL signoff, and emulation flows
• Track record of presenting at industry forums (DAC, SNUG, CDNLive, ISPD) or contributing to EDA standards bodies
• Demonstrated ability to build and lead geographically distributed engineering teams across multiple time zones
• Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.
• Our incl

Additional Information

Annapurna Labs is hiring a Senior CAD Manager to build, lead, and scale the CAD/EDA organization driving RTL-to-GDS methodology, flow development, and analytics across multiple sites. This is a strategic leadership role responsible for defining the multi-year roadmap for digital implementation, signoff, and physical verification; building and scaling a geographically distributed CAD team; and partnering with design, DV, IT, and EDA vendors to enable next-generation SoC tape-outs at advanced nodes (5 nm / 3 nm / 2 nm and below). You will own the technical direction and operational health of the full digital backend toolchain - synthesis, place-and-route, STA, power/IR, EM, and physical verification - along with the license, dashboard, and automation infrastructure that supports it. Success in this role means a CAD organization that materially accelerates time-to-tape-out, raises PPA and signoff quality, and gives engineering leadership data-driven visibility into project health. Key job responsibilities Define and drive the multi-year roadmap for RTL-to-GDS flows across synthesis, place-and-route, STA, signoff, and physical verification; lead methodology bring-up for new technology nodes, foundry PDKs, and IP integration. Own the EDA tool strategy and vendor relationships; lead structured evaluations, benchmarking, license forecasting, peak-load planning, and cost optimization in partnership with procurement and finance. Build and scale the CAD environment - flow frameworks, regression infrastructure, run management, release engineering, CI/CD-style practices, and version control supporting multiple technology nodes. Own the strategy for CAD dashboards and analytics: PPA tracking, run health, signoff QoR trending, tape-out readiness scorecards, and compute/license efficiency metrics. Build, mentor, and scale a multi-site CAD organization; establish operating cadence, technical reviews, knowledge-sharing practices, engineering standards, and quality bars for CAD deliverables. Partner with physical design, DV, RTL, package, IP, and IT teams to align flow capabilities to program commitments; engage executive stakeholders on technology readiness, schedule risk, and capacity planning.

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Company Intel

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