Senior/Staff Layout Engineer (CAD & APR Automation)

About the role

Role Overview We are seeking ahighly skilled Layout Engineer with exceptional CAD capabilities to join ourCustom Layout Engineering team. This role combines hands-on APR layoutimplementation with advanced CAD automation expertise, empowering you toexecute layout designs while revolutionizing productivity through workflowautomation and methodology innovation. Job Description APR Layout Implementation Execute full-cycle APR layout using Innovus, ICC2, or Fusion Compiler for Foundation IP, Analog IP, RFIC, and digital blocks. Serve as the DRI for layout automation flows, including APR implementation, physical verification, and sign-off. Perform floorplanning, power mesh planning, critical block placement, and hierarchical layout construction. Optimize layouts for Power, Performance, and Area (PPA) through iterative refinement. CAD Layout Support & Automation Provide centralized CAD layout support to Foundation IP, Analog/RF, and SoC teams across multiple projects. Create, maintain, and enhance automated layout workflows from development through production deployment. Develop scripting utilities using Python, Tcl, SKILL, and Perl to automate tasks and streamline processes. Build scalable CAD infrastructure, including parameterized cells (P-cells), reusable templates, and modular architectures. Incorporate AI and Agentic AI technologies into layout workflows to boost productivity. Establish standardized CAD procedures and best practices across diverse project executions. Process Node Expertise & Verification Apply backend layout knowledge across planar, FinFET, and GAA process nodes from leading foundries. Master complex DRMs, DFM requirements, and physical verification flows for advanced technologies. Conduct physical verification (DRC/LVS/ERC/ANT/PERC) with expert-level debugging. Ensure layout compliance with EM/IR, SI/PI, and ESD integrity requirements. Create new flows or methodologies to boost team productivity. Job Requirements Bachelor's Degree in Electrical/Electronic Engineering or a related field. Relevant experience in both APR layout implementation and CAD/automation development. Strong CAD capability with a proven track record of workflow, tool, or script development that improves productivity. Hands-on proficiency with APR tools such as Cadence Innovus, Synopsys ICC2, and/or Fusion Compiler. Deep understanding of CMOS layout across planar, FinFET, and GAA process nodes, including DRM and DFM principles. Expert-level physical verification skills, including DRC/LVS/ERC/ANT/PERC debugging using Calibre, PVS, or equivalent tools. Strong scripting proficiency in Python, Tcl, SKILL, and Perl for tool automation and flow development. Knowledge of floorplanning, power mesh planning, critical signal routing, and hierarchical integration. Excellent cross-team communication skills with the ability to support multiple concurrent projects. Familiarity with AI or Agentic AI in EDA workflows. Experience in Foundation IP (IO/ESD), RF/Analog layout, SI/PI analysis, or EM/IR considerations is an added advantage. Interested candidates mayapply through the application system. We regret to inform only Shortlistedcandidates will be notified. By sending us yourpersonal data and curriculum vitae (CV), you are deemed to consent to PERSOLSingapore Pte Ltd and its affiliates to collect, use and disclose your personaldata for the purposes set out in the Privacy Policy available at https://www.persolsingapore.com/policies. You acknowledge that you have read, understood, andagree with the Privacy Policy. PERSOL Singapore Pte Ltd - RCB No. 200007268E - EALicense No. 01C4394 - EA Registration No. R1877971 (Derrick Tiew Yong Han)

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