Senior FPGA Design Engineer

Responsibilities

• RTL design for FPGA, including RTL porting, IP integration, closing timing and generating bit streams
• FPGA simulation setup and testing
• FPGA system setup, validation and debug
• Work with SW team to bringup and validate FPGA system product
• Product experience with FPGAs and related tools such as Vivado and Protocompiler
• Strong experience in RTL design, especially design for FPGAs
• Integration of IPs and CPUs for FPGA
• Experience in RTL simulation testing
• Experience in bringing up and debugging SW on FPGA systems
• Familiarity with PCIe, USB, Ethernet, SPI. The following are pluses: ESPI, SGPIO, LTPI
• Self-driven, good problem solving and communication skills
• BS or MS (preferred) degree in EE/EECS/CS or equivalent.
• At least 5 years of industrial experience
• Axiado is committed to attracting, developing, and retaining the highest caliber talent in a diverse and multifaceted environment. We are headquartered in the heart of Silicon Valley, with access to the world's leading research, technology and talent.

Additional Information

Senior FPGA Design Engineer position is your opportunity to join one of the industry's leading companies in platform security management and ransomware detection for cloud datacenters, 5G infrastructure and disaggregated compute ecosystems. You should have prior knowledge about RTL design, FPGA prototyping and computer architecture. As the Senior FPGA Design Engineer for Axiado, you will have the opportunity to work in design, verification, debug and system integration. You will work closely with the Architecture, Verification, ASIC Design and Software teams, and report into the Engineering organization.

Your Match

How well this role fits your profile.

Company Intel

What employees say

Worked at Axiado? Share your experience