DSP Architecture Engineer

Requirements

• Master's degree and/or PhD in Communication Engineering, Electrical Engineering or related fields. As a plus, 2-5 years of experience with DSP architecture and algorithm development will be appreciated.
• Deep understanding of digital communication and signal processing theory
• Strong experience in communication system modeling and simulation
• Good knowledge of optical communication systems is a plus
• Experience in high-speed DSP and Clock and Data Recovery (CDR) is a plus
• Good programming skills in Matlab/Python/C/C++
• Understanding of digital implementation of DSP is a plus
• Team player who is willing to take on a variety of projects, and self-motivated.
• Expected Base Pay Range
• 47,300 - 63,000, EUR per annum
• The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
• Additional Compensation and Benefit Elements
• All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
• Interview Integrity
• To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
• #LI-AO1

Additional Information

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As Staff System Architecture Engineer you will be part of the R&D group developing next generation serial-link transceivers for electrical and optical applications which will continue to drive the growth of AI and Datacenter communication bandwidth. You will participate to the design, simulation, and optimization algorithms for 100G+ per lane data rates. You will be exposed to many technologies, including 5nm, 3nm, and 2nm developments and you will interact with many different teams. What You Can Expect What You Can Expect Design and simulate DSP architectures, define key capabilities, performance requirements and drive specifications for both analog and digital designers. Develop and simulate DSP algorithms and behavioral models of mixed-signal systems Perform R&D activities in digital signal processing for SerDes and optical channels. Work with designers to ensure circuit architecture can be efficiently implemented. Participate to cross functional teams with analog, digital and firmware designers for bring up and validation/optimization activities

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