IC Package Design / Development

Responsibilities

• Package Architecture, Co-Design & Optimization
• Collaborate with chip design and analog/digital IP/PHY teams (224G/112G SerDes, PCIe Gen 6/7, ADC/DAC, etc.) to optimize chip floorplan, die bump patterns, and IO architecture for advanced node products.
• Co-optimize package stack-up, layer count, escape routing, BGA pattern, and power integrity architecture aligned to system and manufacturing requirements.
• Interpret SI/PI parameters (RL, IL, NEXT/FEXT, etc.) to drive signal integrity optimization.
• Package Design & Integration
• Work with IC design, system engineering, SI/PI, and thermal teams to perform BGA substrate design using Cadence APD or equivalent tools.
• Ensure package designs meet SI/PI, mechanical, high-power thermal and reliability targets.
• Define and refine assembly BOM, process flows, and design rules for advanced packaging technologies.
• Define POR for new silicon nodes including bump metallization, geometry, and process requirements.
• Drive implementation, optimization, and HVM qualification of new package / assembly technologies.
• Program Management & Cross-Functional Execution
• Own packaging deliverables from concept through substrate design, development, qualification, and high-volume manufacturing.
• Lead interactions with assembly, substrate, and manufacturing partners for NPI bring-up and production ramp.
• Provide sustaining support during HVM, including multi-source enablement.
• Work closely with QA, product/test engineering, and customer teams to diagnose and resolve quality, reliability, or manufacturing issues.
• Required Qualifications
• Bachelors and 8+ years or Masters degree and 6+ years or PhD and 3+ years of related experience;
• BS/MS/PhD in Electrical Engineering (Preferred), Mechanical Engineering, Materials Science, or related field.
• Extensive hands-on experience in advanced IC packaging for advanced silicon nodes.
• Expertise in substrate design, SI/PI principles, thermal management, and high-speed IO packaging.
• Strong understanding of high layer count, large body, flip chip BGA packaging technology
• Proficiency in Cadence Allegro APD/SIP or comparable packaging design tools.
• Experience working with global OSATs and substrate suppliers.
• Proven ability to drive NPI through HVM with strong cross-functional leadership.
• Excellent communication, documentation, and customer-facing skills.
• Additional Job Description:
• Compensation and Benefits
• The annual base salary range for this position is $108,000 - $192,000
• This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
• If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Benefits

Additional Information

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: IC Package Design / Development Role Overview We are seeking an experienced IC Packaging Engineer to drive next-generation package architecture, design, and productization using advanced node silicon (7nm, 5nm, 3nm and beyond). This role partners closely with chip design, system design, SI/PI, thermal, and manufacturing teams to define and deliver industry-leading package solutions. The ideal candidate has deep technical expertise in substrate design, floor-planning, bump architecture, advanced materials, and HVM execution.

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Company Intel

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