Principal Test Engineer/DFT Architect

Requirements

• Experience with power-management, automotive, high-voltage, mixed-signal, or digitally assisted analog products.
• Experience with ATE platforms such as Advantest V93K,

Additional Information

Test and DFT Architecture - Define product-level test and DFT strategy, including wafer probe, final test, characterization, qualification, GRR, production test flow, and cost-of-test targets. - Partner with design, systems, validation, product engineering, test engineering, quality, operations, and manufacturing teams to define DFT requirements early in the lifecycle. - Drive requirements for test muxes, scan/debug access, analog observability, digital controllability, embedded monitors, BIST where applicable, trim/calibration access, fuse/NVM test modes, and diagnostic hooks. - Review schematics, architecture documents, specifications, register maps, and test-mode plans to identify testability gaps before design freeze. - Establish reusable DFT and test-access standards for power, analog, mixed-signal, and digitally assisted products. ATE and Production Test Strategy - Define ATE platform strategy, including tester selection, instrument usage, multisite targets, handler/prober compatibility, hardware reuse, test-time optimization, and production scalability. - Establish strategic test flows, binning methodology, screen strategy, guardband approach, data collection strategy, and test naming conventions. - Assess feasibility for critical tests such as high-voltage stress, analog parametric measurements, digital interface testing, trim/calibration, NVM programming, wafer-level characterization, and production diagnostics. - Influence test hardware architecture, including load boards, probe cards, sockets, change kits, and interface circuitry, to improve accuracy, signal integrity, and multisite scalability. - Guide platform-transition strategies and production test readiness for new products and product families. Circuit and Testability Leadership - Apply circuit-level knowledge to ensure key internal nodes, bias conditions, clocks, references, protection circuits, calibration loops, and failure mechanisms are observable and controllable on ATE. - Work with design teams to ensure critical analog, digital, and power-management functions can be accurately measured in production. - Evaluate the impact of circuit architecture, wafer-test strategy, package choice, and test platform capability on test coverage, yield learning, quality risk, cost, and cycle time. - Support complex silicon and production debug by connecting ATE data, bench data, circuit behavior, design intent, process variation, and production yield trends. - Identify testability risks early, including limited test access, insufficient characterization coverage, weak diagnostics, limited traceability, or late test-mode definition. Cross-Functional Influence - Serve as senior technical interface between design, DFT, test engineering, product engineering, validation, quality, operations, and manufacturing partners. - Lead testability reviews at key development gates and ensure issues are resolved before tape-out, qualification, or production release. - Create test architecture documentation, DFT checklists, coverage expectations, production-readiness criteria, and product-family test strategy templates. - Mentor engineers on DFT principles, ATE methodology, debug strategy, and scalable production test development. - Influence roadmap decisions for ATE platforms, test data infrastructure, characterization automation, production analytics, and AI-enabled test optimization. --- - Bachelor's degree in Electrical Engineering, Computer Engineering, or related field; advanced degree preferred. - Typically 12+ years of semiconductor experience in test engineering, DFT, product engineering, validation, design, or product industrialization. - Strong hands-on experience with ATE test development and production test strategy. - Experience with analog, mixed-signal, digital, and/or power-management IC test. - Strong understanding of ATE instrumentation, timing, digital pattern execution, analog measurements, multisite test, handler/prober interfaces, test hardware, and production data. - Working knowledge of circuit design concepts, including references, regulators, ADC/DACs, digital interfaces, clocks, trims, NVM/fuse structures, protection features, and test-access circuitry. - Familiarity with wafer sort/final test strategy, production test flows, yield learning, quality screening, and test-cost modeling. - Ability to read schematics, block diagrams, design specs, register maps, test plans, and characterization/yield data. - Strong debug capability using ATE results, bench measurements, simulation data, failure-analysis inputs, and production trends. - Experience with scripting, automation, and data analysis tools such as Python, JMP, MATLAB, SQL, or equivalent. - Demonstrated ability to lead cross-functional technical reviews and influence without direct authority.

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Company Intel

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