ASIC Design Engineer

Responsibilities

• Assist in designing micro-architecture for ISP and CV algorithms.
• Perform RTL design using Verilog/System Verilog and HLS tools (Catapult).
• Support the analysis of metrics related to power, performance, and area.
• Collaborate with architects and DV Engineers to ensure efficient verification signoff.
• Help with FPGA tasks, including emulation, validation, and debugging.
• Qualification/ Requirements:
• Education: Minimum Master's degree and above in Electrical/Electronics/Computer Engineering.
• Experience: Entry-level position; relevant coursework or project experience in ASIC design or image signal processing is a plus.
• Technical Skills:
• o Experience/knowledge in Verilog/SystemVerilog and C/C++.
• o Familiarity with ASIC design processes and frontend design.
• o Knowledge of image/vision/video data processing or algorithm acceleration is beneficial.
• o Familiarity with scripting languages (Python, Perl, Tcl) is a plus.
• Soft Skills: Strong teamwork and communication skills.
• Additional Notes: Strong analytical skills and a willingness to learn and adapt in a dynamic environment.

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Company Intel

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