Software Engineer II: PCle VIP R&D

Requirements

• Complete Bachelor's degree in Computer Science and experience or a related technical field with relevant experience.
• Extensive experience in modeling in C/C++ and background in object-oriented, algorithms, and data structures.
• In-depth understanding of complexity, analysis graph algorithms, and advanced debugging techniques for proficiency in troubleshooting software issues and debugging a large codebase.
• Strong analytical and problem-solving skills with an ability to visualize processes and outcomes.
• Outstanding all-round communication skills and ability to work collaboratively in a dynamic multi-location environment.
• English and Portuguese language communication.
• Working knowledge of PCI Express (PCIe) protocol or one or more protocols USB, NVME, SATA, Display Port, etc.
• Knowledge of Verilog/System Verilog languages and OVM/UVM verification methodologies.
• Experience with digital logic design or IP/SoC level Verification flow.
• Customer orientation and knowledge of the EDA tool flow.
• Additional Job Details:
• Employment category: CLT
• Employment term: 40 hours/week.
• Competitive benefits.
• Location: Av Contorno 5800, Belo Horizonte, Minas Gerais Brazil.
• About Cadence Design Systems:
• We're doing work that matters. Help us solve what others can't.

Additional Information

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence Design Systems Inc. is looking for a motivated Software Engineer II: PCle VIP R&D to work with us in Belo Horizonte, Brazil. At Cadence, we hire and develop leaders and innovators who want to impact the world of technology. Cadence has been nominated as a Great Place to Work globally and in Brazil and is also a Fortune 100 Best Companies to Work For . As a Software Engineer II, you will be part of VIPPCIE R&D team in the SVG group in Belo Horizonte, Brazil. The VIPPCIE R&D team works with PCIe verification IP. To understand more on what we do, you can visit PCIe VIP at Cadence . Working at Cadence is very dynamic, fast-paced, and integrated with other teams all around the world. Job Description: The Software Engineer II will be responsible for software development (C/C++) and validation of PCIe Verification IP. The Software Engineer II is expected to participate in development efforts of the PCIe product to meet customer use model, solution requirements, protocol specification and execute necessary SW development practices to create reusable robust software solution to enable verification of these interface protocols. Candidate should be able to work with multi-site and diverse team. You need to effectively collaborate multi location development team to contribute in PCIe verification IP development, milestones technical roadmap and people training for success

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