Senior Staff Engineer, ASIC/VLSI Synthesis and Design

Requirements

• Bachelor's degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience OR Master's degree and/or
• PhD in Computer Science, Electrical Engineering or related fields with 3-5 years
• of experience.
• Minimum of 5 years of industry experience in ASIC implementation and synthesis.
• Strong understanding of ASIC design flows, from RTL to GDSII.
• Knowledge and hands-on experience with synthesis and STA methodologies and implementation.
• Proficiency in using synthesis tools, STA tools, and scripting languages (e.g., Tcl, Perl).
• Experience with high-complexity silicon in advanced technology nodes, preferably TSMC N4/N5.
• Strong understanding of timing constraint development for hierarchical designs.
• Experience doing functional ECOs using industry standard tools and flows like Conformal ECO.
• Experience with UPF development for blocks and SoCs. UPF validation using tools like Conformal Low Power (CLP)
• Familiarity with physical design and timing optimization techniques and strategies to achieve timing cl

Additional Information

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOC) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system interconnect bandwidth, memory bandwidth, and memory capacity. Marvell's Photonic Fabric™ is the next-generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions. The Photonic Fabric™ is available to our customers in multiple technology offerings, including optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB). This allows customers to easily incorporate high bandwidth, low power, and low latency optical interfaces into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging processes. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies. This innovation empowers hyperscalers to enhance the efficiency and cost-effectiveness of AI processing by optimizing the XPUs required for training and inference, while significantly reducing the TCO2 impact. To bolster customer collaborations, Marvell is developing a Photonic Fabric ecosystem consisting of tier-1 partnerships that include custom silicon/ASIC design, system integrators, HBM memory, assembly, and packaging suppliers. What You Can Expect We are seeking a highly skilled and experienced synthesis and ASIC front-end implementation Engineer to join our team. The ideal candidate will have a strong background in timing constraints development, synthesis and front-end implementation flows & methodologies for both SOC level and block level. They should have experience that includes logic synthesis (MMMC synthesis), logic equivalency checks, STA, timing constraints, functional ecos, hard IP integration, timing budgeting, optimization and timing closure of high-speed designs. Additionally, experience with deep technology nodes such as 5nm/4nm would be valued. Develop and validate timing constraints for intricate SoC designs. Collaborate with Architecture, RTL, DFT, and Analog teams to understand the design requirements, analyze the timing complexities, and develop consolidated timing modes and constraints for synthesis, PnR and chip timing sign-off flows. Own and contribute to various Front-End Implementation tasks & flows like Synthesis, UPF development, Logical Equivalence Checks (LEC), Functional ECOs, etc. Analyze and understand the tradeoffs between power/performance and area goals to drive them into overall chip implementation flows. Perform Physical Aware Synthesis using industry-standard tools like Fusion Compiler. Resolve or find workarounds for tool issues, independently or working with EDA tool vendors. Automate Front End Flows and processes using scripting languages such as Tcl or Python. Ensure compliance with Netlist Handoff checklists and criteria for delivery to PD. Document best practices and lessons learned to drive continuous improvements in future projects.

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