Sr Principal ASIC Design Engineer - Terawave

Requirements

• BS, MS in Electrical Engineering or a related technical discipline
• 15+ years of experience
• Deep working knowledge and hands-on experience in innovative verification flows
• Base Pay Range for:
• CA applicants is $308,051.00 - $431,270.70
• WA applicants is $308,051.00 - $431,270.70
• Other site ranges may differ
• Culture Statement
• Export Control Regulations
• Applicants for employment at Blue Origin must be a U.S. citizen or national, U.S. permanent resident (i.e. current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.
• Background Check
• Required for all positions: Blue's Standard Background Check
• Required for Certain Job Profiles: Defense Biometric Identification System (DBIDS) background check if at any time the role requires one to be on a military installation

Benefits

Additional Information

Application close date: Applications will be accepted on an ongoing basis until the requisition is closed. At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We're working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight! Blue Origin is pioneering the future of space-based communications with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This multi-orbit constellation will consist of optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO), providing enterprise-grade connectivity for critical operations worldwide. We are seeking ASIC/SOC Design e ngineer s (levels including Principal, Senior Principal) who are critical to ensuring our RFIC/ASIC design s culminate in thoroughly designed and validated cutting-edge integrated circuits that drive Blue Origin's mission of enabling millions to live and work in space for the benefit of Earth. Location: This role is based on site in San Diego, CA; Bay Area, CA; Austin, TX; Kent, WA. This role requires a highly skilled Design and Verification Engineer with extensive experience in complex SoC design, integration, and verification. The candidate will be responsible for driving end-to-end design and verification methodologies, from writing requirements and specifications to post-silicon bring-up. Strong expertise in Verilog/System Verilog, DSP structures, modem SOCs, ARM CPU integration, and interface protocols is essential, along with the ability to optimize performance and power, support back-end teams, and ensure seamless portability across FPGA and silicon environments. Design and Verification Verilog/System Verilog experience in designing complex SOCs CDC, RDC, LINT Write requirements, specifications and test plans Optimize performance while keeping power low Clock gating (dynamic and static) Multi-voltage SOC front end design Formal verification Functional coverage, definition and collection Module verification Complex subsystem verification Complex SoC verification Co-simulation with software, integration of software build tool flow with simulation Gate simulation External IP integration ARM CPU single and multi-core integration with bus fabric, GIC, cache, MMU, secure boot AXI bus complex High performance DMA NOC integration DDR, PCIE, Ethernet, SPI integration High speed serdes integration DSP structures (FIR, Cordic, FFT/IFFT, MAC, circular buffers, analog-digital interface) Modem using state of the art DSP, coding, framing (phy and MAC) Sequenced and time bound data movement in DSP structures (time slots, time stamps etc) SOC top level integration using models for analog macros Verification using golden reference models in Matlab, SystemC or C Code coverage Timing constraints Support back-end teams during DFT, LEC, floorplan, STA Post-Silicon Post silicon bring up FPGA ASIC to/from FPGA flow

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