Defectivity Process Engineer (JR12215)

Responsibilities

• Analyze defect Pareto, defect maps, and characterization data to identify root causes and containment actions.
• Drive tool OOC reduction and lead sporadic defect reduction activities.
• Lead the troubleshooting of defectivity alert and involve in Material Review Board for material assessment and disposition.
• Support troubleshooting of defectivity alerts and escalation of critical issues.
• Work closely with process, equipment, device, quality, and production teams to drive defect reduction and line stability.
• Support technology transfer and industrialization activities to ensure smooth deployment of new products and processes.
• Responsible for setting up, optimizing, maintaining Process Defectivity Systems like Automation system (Auto defect sampling, Auto DOI, DOLI), Defect library.
• Opportunity to involve in deployment of Advanced Defectivity Monitoring system involving AI, Convolution Neural Network (CNN) and deep learning with DIT team and opportunities to learn and apply data analytics.
• Skills and Competencies
• Degree in Material Science/Electrical/Electronics/Microelectronics/Mechanical/Physics/Chemistry.
• Preferred minimum 3 years working experience in semiconductor wafer fabrication industry and good knowledge in Defectivity methodology and knowledge of Defectivity inspection tool. Fresh graduate is welcomed to apply as well.
• Knowledge in Klarity Defects/AceXP/Space/Spotfire and other Defectivity related tool will be an added advantage.
• Strong analytical and problem-solving skills.
• Good understanding of semiconductor wafer fab processes.
• Ability to work across departments and communicate clearly.
• Proactive mindset with strong ownership and teamwork.
• Self-driven and independent with an inquisitive mind.
• Familiar with SPC concept and other problem-solving tools: SPACE, FMEA, 8D, Data mining analysis and AI base on Convolution Neural Network (CNN) will be advantageous.

Additional Information

The Defectivity Line Control Engineer is responsible for controlling defectivity in semiconductor wafer fabrication through daily line monitoring, OOC management, tool excursion response, and cross-functional problem solving. The role supports both routine operations and improvement activities to ensure stable process performance, product quality, and effective industrialization.

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Company Intel

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