Design Verification, Senior to Staff Engineer

Requirements

• BS/MS/PhD Degree in Electrical Engineering / Computer Engineering / Electronics and Telecommunications Engineering, or a related field.
• Proficiency in verification languages such as SystemVerilog, UVM, and scripting languages (Python, Perl, etc.).
• Understanding of ASIC design flow, strong understanding of digital design and verification methodologies.
• Experience with industry-standard EDA tools (e.g., Cadence, Synopsys, Mentor Graphics).
• Strong mathematical skills.
• Strong problem-solving skills.
• Fluent in English language, excellent communication skills,
• Preferred Qualifications: Experience with high-speed Serdes/PHY interfaces design/design verification.
• Additional Compensation and Benefit Elements
• Competitive salary, plus 13th-month salary and performance-based bonus
• RSUs (Restricted Stock Units) for new joiners and on-going annually
• Premium health & accident insurance for you and your family (spouse and children)
• Annual medical check-up at a designated hospital arranged by Marvell
• Generous paid leave policies: 15 annual leave days, 3 Recharge periods per year (company-wide off-work from Friday to Monday), 5 paid sick leave days, 3 days of volunteer time-off and 11 public holidays
• Exciting Employee Events: Participate in fun activities throughout the year such as team birthdays, sports tournaments, company trips, mid-autumn, appreciation week, charity, health seminars, year-end party, and more.
• All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
• Interview Integrity
• To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
• #LI-UN1

Benefits

Additional Information

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell Compute and Custom Solutions has been at the forefront of developing and delivering leading-edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast-growing product lines, Marvell technology is powering the next-generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Automotive Compute market segments. What You Can Expect Develop and implement verification plans for Serdes/PHY chip designs. Create and maintain testbenches using industry-standard verification tools and methodologies. Perform functional and performance verification of complex digital designs. Collaborate with design and architecture teams to identify and resolve design issues. Analyze and debug simulation failures and provide detailed reports on verification results. Mentor and guide junior verification engineers.

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