Coherent Fabric Design
External$198K–$268K/yrFull-timeOn-site3d ago
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About the role
Design RTL logic for a coherent interconnect fabric using SystemVerilog. Collaborate with verification, implementation, performance, and power teams to deliver high-performance, low-power IP. Track and coordinate tasks, debug functional and performance issues with simulation and tools, and improve design methodology across the System IP group.
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Company Intel
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