ASIC Engineer - SDC

Responsibilities

• Own and develop full-chip timing constraints (SDC) across functional and test modes for complex networking SoCs.
• Drive Static Timing Analysis (STA) and partner with RTL, physical design, and DFT teams to resolve timing issues across the design hierarchy.
• Partner with RTL designers to achieve timing convergence through constraint development and timing-driven RTL improvements.
• Define and maintain clocking architectures and constraint models, including clock groups, timing exceptions, and clock exclusivity.
• Integrate and validate timing constraints from third-party IP vendors within the full-chip SoC timing environment.
• Develop and review block-level SDCs and clocking architectures, ensuring constraint correctness and alignment across the design hierarchy.
• Contribute to timing closure and silicon readiness across multiple modes, corners, and operating conditions.

Requirements

• Bachelor's degree in Electrical or Computer engineering and 7+ years of ASIC experience, or Master's degree in Electrical Engineering or Computer Engineering and 4+ years of ASIC experience, or PhD in Electrical Engineering or Computer Engineering +1 years of ASIC experience.
• Experience developing block-level and full-chip SDC constraints for complex SoC designs.
• Expertise in Static Timing Analysis (STA) using tools such as Synopsys PrimeTime or Cadence Tempus.
• Experience writing timing constraints for complex networking SoCs and ARM CPU subsystems.
• Experience integrating third-party IP timing constraints into full-chip SDC environments.
• Understanding with RTL design and synthesis, with the ability to analyze RTL structures and guide timing-driven design improvements.
• Experience developing constraints for large SoCs with multiple clock domains and complex clocking architectures.
• Ability to analyze RTL structures and recommend timing-driven micro-architectural improvements.
• Expertise with constraint analysis tools (Synopsys TCM, Cadence CCD) and CDC analysis tools (SpyGlass CDC).
• Proficiency in engineering scripting and automation (Python, Perl, TCL).
• Why Cisco?
• We are Cisco, and our power starts with you.
• Message to applicants applying to work in the U.S. and/or Canada:
• The starting salary range posted for this position is $165,000.00 to $241,400.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Benefits

Additional Information

The application window is expected to close on: 07/10/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . This role requires being onsite in San Jose, CA at least 4 days/week Meet the Team The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco's core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms-like Silicon One-are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development-from design to qualification to production-is within our team, we're able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

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Company Intel

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