Technical Manager, IC Physical Design

Responsibilities

• IC physical design of 6nm/4nm/3nm and below world leadinga dvanced process chip, from RTL to GDS.
• Block coordinator role for Synthesis/APR/PV tasks of more than10 blocks, solving the critical issue and give the solution to block owners.
• TOP role for the complicated hierarchical chip (more than 20million instances plus 1000+ macros), doing floorplan, partition and assembly etc.
• PD PM role to coordinate with Frontend and Signoff team about on time delivery of the SoC PD tasks, responsible for full chip PD schedule and tapeout.

Requirements

• Strong knowledge of IC design, leader role with tapeout experience is a must
• With a minimum of 8 years of experience
• Strong knowledge of UNIX/LINUX env and capable of at least one of the following programming language: C/C++, Python, TCL, Perl
• Excellent communication and teamwork spirit, could coordinate with different teams to conquer all gating items, drive team to finish the assigned task on time with quality
• Interested candidates may apply through the application system. We regret to inform only Shortlisted candidates will be notified.
• EA License No. 01C4394 - RCB No. 200007268E -EA Registration - Lim Jia Jie EA Registration No. R22108969

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Company Intel

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