Mixed Signal IP Verification Engineer

Requirements

• Minimum qualifications are required to be initially considered for this position.
• A Bachelor's or BS degree and/or equivalent knowledge in a specialized field, with at least 3 years of relevant experience,
• OR A Master's degree and/or equivalent knowledge in a specialized field, with at least 2 years of relevant experience,
• OR PhD and/or equivalent knowledge in a specialized field, with at least 1 year of relevant experience,
• Experience listed above should be a combination of the following:
• Verification methodologies such as OVM and UVM.
• System Verilog and Verilog for test environment and design verification.
• Developing test environments for functional verification of mixed signal logic components.
• Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
• Experience with power intent design and/or UPF (Unified Power Format) modeling.
• Intel offers a dynamic and inclusive environment where your expertise will be valued, your contributions will make a difference, and your career will thrive. Join us in driving technical excellence and building the future of computing technologies.
• Apply today.
• Job Type:
• Experienced Hire
• Shift:
• Shift 1 (United States of America)
• Primary Location:
• US, California, Folsom
• Additional Locations:
• US, California, Santa Clara, US, Colorado, Fort Collins, US, Oregon, Hillsboro
• Business group:
• Posting Statement:
• Position of Trust
• N/A

Benefits

Additional Information

Job Details: Job Description: Join Intel as a Mixed Signal Design Verification Engineer and play a crucial role in shaping the future of cutting-edge technology. In this role, you will be at the forefront of ensuring Intel's mixed signal logic components meet the highest standards of functionality, performance, and reliability. As part of a world-class team, your work will directly contribute to the design of advanced architectures and technologies that will power tomorrow's innovations. Responsibilities will include but are not limited to: Develop and execute comprehensive verification plans for mixed signal logic components to ensure alignment with microarchitecture specifications. Design and implement test benches and verification environments using advanced methodologies such as OVM and UVM. Perform system-level simulation to verify functionality, analyze power and timing, and identify potential design issues. Collaborate with digital and analog architects, RTL developers, and physical design teams to optimize verification strategies and meet performance, power, and functional goals. Debug presilicon issues by replicating, root causing, and implementing corrective measures for failing tests. Create and maintain analog behavioral models and contribute to the development of reusable verification infrastructure and methodologies. Document test plans, verification results, and drive technical reviews with design and architecture teams. The ideal candidate should show the following behavioral traits: Exceptional problem-solving skills, willing to debug complex presilicon issues. Strong collaboration and communication skills, with a track record of working effectively with cross-functional teams. Passion for innovation and a commitment to excellence in engineering.

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