Senior ASIC DV Engineer
External
Broadcom · Usa-ca San Jose Innovation DrivePrepare for this interview
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Requirements
- Bachelors and 12+ years of related experience; or Masters degree and 10+ years of related experience; or PhD and 7+ years of related experience
- MS or PhD is preferred
- Additional Job Description:
- Compensation and Benefits
- The annual base salary range for this position is $141,300 - $226,000 .
- This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
- If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Benefits
Additional Information
Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: You will contribute to the development of complex SOCs targeted towards Touch Controllers/Wireless Charging Chips and other new initiatives. As a verification engineer, your responsibilities will include: Architecting block and full-chip verification environments using HVLs (UVM) and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Using your thorough knowledge of mixed-signal simulations (AMS, Spice, etc), developing test plans and coverage metrics from specifications and writing block and chip-level tests. Debugging RTL and Gate simulations and work with design engineers to verify fixes. Writing diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC. Replicating silicon bugs in simulation environments and validating fixes or SW workarounds. Converting verification tests to test patterns and assisting Test Engineers on ATE vector bring up. Evaluating latest verification methodologies and developing scripts etc. to automate verification flows. Experience understanding and verifying low power silicon for mobile applications with good knowledge of UPF low power verification flow Ability to take customer requirements to verify full chip design and architecture
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