Senior Physical Design Engineer for Core IP

Requirements

• Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
• Note:
• This position is not eligible for Intel immigration sponsorship.
• Minimum Experience and Qualifications:
• Bachelors in Computer/Electrical Engineering or related field with 10+ years of relevant work experience. Or a Masters in the same filed with 5 + years of relevant work experience.
• You must have 10+ years of experience in:
• Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure
• PV convergence (including static timing and power analysis)
• Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks
• Scripting in an interpreted language, minimum TCL in addition to at least one other (e.g. Perl, Python, Ruby)
• Demonstrated success in one or more of the following areas: Synthesis of a digital logic block, which was integrated into a large SoC or IP
• Preferred Experience and Qualifications:
• Physical design best known practices concerning floor-planning, routing techniques, clock distribution
• Static Timing Analysis, Noise analysis, and reliability verification techniques
• RTL to GDS methodologies and formal equivalence
• Synopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence (genus/innovus)
• Perform CPU level timing analysis and optimization, ensuring designs meet functional and performance requirements
• Generate and verify timing constraints while addressing timing violations at the chip or block level for CPU cores
• Work closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning
• Job Type:
• Experienced Hire
• Shift:
• Shift 1 (United States of America)
• Primary Location:
• US, Oregon, Hillsboro
• Additional Locations:
• Business group:
• Posting Statement:
• Position of Trust
• N/A

Benefits

Additional Information

Job Details: Job Description: As a member of CPU development team, you will have a front seat in designing the latest core IP to power cutting edge compute processors across client, server, IOTG and AI. We innovate state of the art microprocessor architecture on the most advanced and latest process technologies with a focus on power efficiency. Our core designs are present in nearly all segments of intel's compute roadmap. As a Senior Physical Design Engineer for Core IP your responsibilities include: Synthesis and Place and Route using industry standard tools for high speed CPU core design Perform all aspects of design flow from logic synthesis, place and route, FEV, power, timing, quality checks, and design closure Develop strategies to deliver reproducible design convergence results Help to create and refine synthesis flow for the project team, Develop and recommend better design method practices to enable better synthesis convergence The ideal candidate will exhibit behavioral traits that demonstrate : Willingness to work with others in a highly complex decision space Skills at developing an implementation plan monitoring key indicators and communicating resource needs and scoping risk to deliver value on schedule Excellent verbal and written communication and collaboration skills

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