Design Verification Engineer - UVM, Verilog (5 to 8 yrs)

Responsibilities

• As a design verification engineer, develop robust test benches, coverage plans, and constrained random tests.
• Ensure high-quality and reliable FPGA/ASIC designs through sophisticated verification techniques and comprehensive debugging.
• Contribute to the adoption and evolution of ground breaking verification methodologies like UVM/VMM, improving team efficiency and performance.
• Partner with architects, logic designers, and software engineers to align on architecture, micro-architecture, and system-level requirements.
• Play a pivotal role in delivering next-generation, high-performance FPGA and ASIC products for Cisco's networking solutions.
• Ensure product reliability and performance, strengthening Cisco's reputation and customer trust in its hardware solutions.

Requirements

• Bachelor's Degree / Master's Degree in Electrical or Computer Engineering with 7+ years of experience in design verification.
• Proficiency in OOPs, Verilog & System Verilog.
• Confirmed verification skills : FPGA, planning, problem solving, debug, adversarial testing and random testing
• Project based work experience with UVM/VMM methodologies.
• You will have experience with architecting the testplan & test bench.
• Hands on experience with Ethernet based protocols, PCIe, AXI, memory controllers, OTN etc. will be an added advantage.
• Familiarity with VCS simulation flow, knowledge of coverage & assertions is desirable.
• Why Cisco?
• We are Cisco, and our power starts with you.

Benefits

Additional Information

Meet the Team We are part of the Hardware Platform Group, with our team specializing in FPGA verification. Our work spans both sophisticated data-path and challenging control-path FPGAs. The verification process includes crafting the DV architecture, test plan, and coverage plan, all the way through to final DV sign-off. We leverage industry-standard tools for simulation, linting, coverage, and assertions, incorporating various quality metrics to ensure a robust process. Our ultimate goal is to deliver bug-free RTL for first-pass success on the board. Additionally, we collaborate closely with our remote teams based in SJC and

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Company Intel

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