Senior/Staff STPG Product Engineering - Probe

Responsibilities

• Probe Coverage Strategy & Ownership
• Define and own probe coverage intent by mapping design features, device behavior, and process risks into probe observability, screening mechanisms, trims, and guard‑bands.
• Define, release, and sustain probe test flows from first silicon through qualification and HVM, ensuring coverage objectives are met without unnecessary test overhead.
• Establish probe limits and guard‑bands based on silicon characterization, design intent, and customer specifications, with clear alignment to downstream test.
• Lead probe enablement for new product introductions (NPI) and technology ramps, identifying coverage and manufacturability risks early and driving mitigation plans.
• Pre‑Silicon Design‑to‑Probe Staging & DFT Readiness
• Partner with Design, DFT, and DV teams during pre‑silicon phases to drive effective design‑to‑probe staging.
• Review and influence DFT architecture, test hooks, observability, redundancy, and trim structures to enable efficient and manufacturable probe coverage.
• Participate in pre‑silicon verification and simulation reviews to reduce first‑silicon debug risk.
• Define probe coverage intent early and ensure continuity from design features through probe and downstream test (shift‑left learning).
• First Silicon Bring‑Up & Device Characterization
• Support first‑silicon bring‑up using engineering probe platforms and lab‑based characterization setups.
• Perform silicon and device‑level characterization (parametric behavior, margins, trims, stress response) to inform probe limits and screening strategy.
• Correlate early silicon behavior with probe results to validate coverage intent, identify gaps, and eliminate redundant content.
• Provide early silicon learning to accelerate probe flow stabilization and yield ramp.
• Yield, Quality & Reliability Enablement
• Drive wafer‑level yield learning, bin definitions, and failure‑mode analysis at probe.
• Enable intrinsic and extrinsic screening strategies in collaboration with Reliability teams.
• Provide structured, data‑backed feedback to Fab, Process Integration, Design, and DV teams to close learning loops efficiently.
• Test Efficiency & Cost Optimization
• Drive test efficiency improvements through coverage right‑sizing and flow optimization, aligned to product and market needs.
• Support wafer‑level speed (WLS) activities as part of broader probe optimization efforts.
• Balance coverage, yield, quality, and cost trade‑offs using silicon data and product risk understanding.
• Data, Analytics & AI Enablement
• Leverage probe, inline, and reliability data for yield analysis, anomaly detection, and decision support.
• Contribute to AI/ML initiatives such as predictive probe, smart sampling, and test optimization.
• Apply data‑driven insights to continuously improve probe effectiveness and efficiency.
• Artificial Intelligence
• Using, applying, and leveraging AI, identify opportunities to streamline workflows, optimize processes, and support innovation by incorporating AI-driven solutions and enabling data-driven decision-making across projects and teams
• Experience Level & Entry Consideration
• This role is open to both early‑career and experienced engineers, with leveling (GJS) aligned to technical depth, scope of ownership, and demonstrated impact.
• Fresh Bachelor's/Master's / PhD Graduates
• Strong fundamentals in semiconductor devices, circuits, physics, or process technology.
• Academic, research, or internship exposure to silicon behavior, characterization, variability, reliability, or design analysis.
• Will grow into full probe ownership with mentorship, focusing on device, design, and process understanding.
• Experienced Engineers (Eligible for Higher GJS)
• Prior experience in product engineering, device engineering, process integration, silicon characterization, or design‑facing roles.
• Demonstrated ownership of first‑silicon learning, qualification strategy, yield mechanisms, or cross‑functional technical trade‑offs.
• Comfortable influencing upstream and downstream teams through technical insight and silicon‑based decision‑makin

Additional Information

The Probe Product Engineer in STPG Product Engineering owns probe strategy and silicon learning at wafer test, spanning pre‑silicon design‑to‑probe staging, first‑silicon bring‑up, qualification, and high‑volume manufacturing (HVM). This role is accountable for defining probe coverage intent, establishing limits and guard‑bands grounded in silicon behavior, and driving yield, quality, and test‑cost outcomes. The focus is on interpreting design intent, device operation, and process interactions, and translating product risk into robust, manufacturable probe strategies aligned with downstream test and customer requirements. The engineer works closely with Design, DFT, Design Validation (DV), Process Integration, Backend Test, and Reliability teams to ensure probe solutions are technically sound, scalable, and product‑centric across the lifecycle.

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Company Intel

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