IP Release Principal Engineer

Responsibilities

• Static Analysis & RTL Quality
• Own the full RTL static analysis sign-off flow including Lint, CDC (Clock Domain Crossing), and RDC (Reset Domain Crossing) checks using Industry standard tools.
• Review and approve RTL static waivers; ensure all waivers are justified, documented, and included in the IP release package.
• Synthesis
• Drive front-end synthesis readiness for each IP subsystem using multiple EDA tools; validate synthesis scripts, timing constraints (SDC), and UPF.
• Work with IPSS COE Implementation Engineers to alidate that IP releases meet synthesis quality bars: clean Analyze/Elaborate, no unconstrained endpoints, and representative PPA metrics (area, timing, power).
• DFT (Design for Test)
• Ensure early DFT consideration is built into each IP subsystem - including scan insertion readiness, BIST hooks, JTAG, and boundary scan.
• Review RTL DFT handoff collateral (filelists, SDC, CDC constraints for DFT), and validate that IP packages are DFT-ready for downstream insertion flows.
• Serve as COE liaison to DFT teams; triage DFT-related blockers for IP releases and drive resolution across design and DFT engineering teams.
• IP Delivery Checklist & Release Qualification
• Ensure alignment of IP releases with requirements and delivery standards.
• Validate IP release packaging through IPMP and ensure versioned, traceable releases are distributed to SoC teams and external customers.
• Maintain and publish IP release quality dashboards and metrics (delivery status, checklist completion, open issues).
• First Line of Support for IP Delivery
• Act as the primary technical point of contact for SoC integration teams consuming COE IP subsystems - triaging and resolving IP integration issues related to static checks, synthesis, and DFT.
• Manage IP delivery escalations; track bugs and action items in Jira; provide timely updates to consuming program teams.
• Provide integration guidance (RTL guidelines, constraints usage, CDC/RDC methodology, synthesis configuration) to SoC engineers adopting COE IP subsystems.
• Interface with third-party IP vendors to review quality metrics (Lint/CDC/RDC results, synthesis reports, DFT support) as part of IP onboarding and evaluation.
• Cross-Functional Collaboration
• Collaborate closely with TFM team, Central Engineering, SoC teams, DFT, PD, FW/SW, and emulation teams to ensure IP packages meet all downstream requirements.
• Participate in methodology working groups to align on Lint/CDC/RDC rule sets, tool selection, and checkpoint requirements.
• Contribute to AI automation to reduce manual effort and increase consistency of IP release flows.

Requirements

• Bachelor's degree in Computer Science, Electrical Engineering

Additional Information

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Custom Compute and Storage (CCS) Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. The SubSystem Physical Implementation Center of Excellence (CoE) team is key part of this group, with global ownership and responsibility for delivering reference Floor Plan for the Sub Systems to the SOC customers. As part of the Implementation CoE team, you will drive the SubSystem Implementation/Back End strategy and PD execution for a high-quality SS design delivery to SOC customers. What You Can Expect The IP Release Principal Engineer is a senior technical individual contributor within Marvell's IP Subsystem (IPSS) Center of Excellence (COE). This role is the quality gatekeeper and first line of technical support for all IP subsystem deliveries - ensuring that every IP package released to SoC integrators and external customers meets Marvell's stringent quality, completeness, and methodology standards. The engineer will own and drive the complete front-end release qualification flow - from RTL static checks through synthesis readiness and DFT enablement - and will serve as the primary point of contact for IP delivery questions, issues, and triage across COE teams and consuming SoC programs.

Your Match

How well this role fits your profile.

Company Intel

What employees say

Worked at Marvell? Share your experience