ASIC Design Verification Engineer, Technical Leader

About the role

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco's core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms-like Silicon One-are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development-from design to qualification to production-is within our team, we're able to think differently, experiment more, and work quickly. Join us to power the future of the digital world. Who You'll Work With: You will be in the Silicon One development organization as an ASIC design verification engineer in San Jose, CA. You collaborate closely with verification engineers, designers, hardware and cross-functional teams to verify the ASIC in simulation, in emulation, and during ASIC bring-up.

Responsibilities

• Maintaining existing DV environments and enhancing them
• Construct test bench including scoreboard, agents, sequencers, and monitors for new blocks
• Write test plan, develop test cases, debug regression failures and drive to module verification closure
• Ensuring complete verification coverage through implementation and review of code and functional coverage
• Use AI tools to develop innovative methods and processes to improve quality of design verification.

Requirements

• Bachelor's with 8+ years or Master's degree with 6+ of relevant experience required; prior experience with System Verilog and UVM methodology
• Prior experience in verifying complex blocks, cluster, and/or top level for ASIC/SoC
• Prior experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes.
• Prior experience with functional coverage and constrained random DV environments.
• Scripting skills: Perl and/or Python scripting
• Strong domain experience in one or more protocols is a plus - PCIe, CXL, Ethernet, AHB/AXI, DDR, MMU.
• Experience with Veloce/HAPS is a plus
• Formal verification (iev/vc formal) knowledge is a plus
• Why Cisco?
• We are Cisco, and our power starts with you.
• Message to applicants applying to work in the U.S. and/or Canada:
• The starting salary range posted for this position is $183,800.00 to $263,600.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
• U.S. employees are eligible for paid time away as described below, subject to Cisco's policies:
• 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
• 1 paid day off for employee's birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
• Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
• Exempt employees participate in Cisco's flexible vacat

Benefits

Additional Information

The application window is expected to close on: 07/31/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . This role will work onsite out of our San Jose, CA office.

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