Senior Technologist, ASIC Development Engineering (IO Design)

Requirements

• Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering
• Working experience (20+ years) in IO including 5+ years as a project leader
• Should have architected and lead high speed interface design solutions from specification through Silicon debug and characterization
• Should have hands-on experience in TX and RX design architectures for high speed applications such as DDR4/DDR5/LPDDR4/LPDDR5 along with timing budget analysis.
• Should be experienced in high speed design architectures such as SERDES, Equalization schemes
• Should have hands-on experience in IPs such as SSTL, LVDS, I2C, POD IOs, PVT calibration, HV tolerant and Fail-safe IOs, Crystal oscillator etc.
• Should have extensive experience in ESD circuits design, Associated ESD guidelines and recommendations in different process nodes, IO and SOC level ESD review and signoff
• Experience in full custom high speed data path design such as DDR PHY will be of advantage.
• Conversant with tools such as Cadence Virtuoso/Synopsys custom compiler/Hspice/Spectre/Finesim including statistical simulation methodologies
• Experience in Mixed-mode simulation and analog/digital co-simulation will be of added advantage.
• Experience in creating EDA model such as Verilog model, Liberty etc will be of added advantage.
• Should have deep understanding and working knowledge of CMOS process including FINFET technologies such as 16nm/7nm/5nm and the associated DFM issues.
• Very analytical in nature and able to work in a multi-disciplinary environment
• Creative, out-of-the-box thinker with a high level of personal involvement
• Strong theoretical background with a pragmatic approach.
• Good verbal and written communication skills and experience working with different geographies.
• Good mentoring, documentation and presentation skills
• All your information will be kept confidential according to EEO guidelines.

Additional Information

Developing best-in-class architecture for Analog Mixed Signal IPs and high-speed parallel PHY interface solutions for next generation NAND flash memory controllers in advanced CMOS technology nodes. Interact with cross-functional teams to define requirements/specs, conceive the optimal solution by evaluating architectures, drive implementation, closely work with layout designers in guiding and reviewing the layouts, ensure timely and high-quality deliverables, extend SOC integration support and review and provide support for post-silicon activities from IP characterization to yield improvement and RMA. Provide good technical leadership in problem solving, planning and mentoring junior and senior engineers. Propose innovative design solutions and design methodologies. Fostering innovation culture and developing efficient processes by adopting state-of-the-art technologies.

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Company Intel

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