Staff Physical Design Engineer

Requirements

• Bachelor's, Master's, or PhD degree in Electronics, Computer Engineering, or a related field.
• 5+ years of progressive experience in back-end Physical Design and Verification and/or Static Timing Analysis.
• Expertise in full-chip & sub-hierarchy integration.
• Experience integrating and taping out large designs utilizing a digital design environment.
• Good understanding of RTL to GDS flows and methodology.
• Good scripting skills in TCL, Linux shells and Python. Familiarity with GIT is a plus.
• Good understanding of digital logic and computer architecture
• Good communication skills and self-discipline contributing in a team environment.
• Experience with multi-voltage and low-power design techniques is a plus.
• Expected Base Pay Range
• 234,800 - 313,000, RON per annum
• The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
• Additional Compensation and Benefit Elements
• All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
• Interview Integrity
• To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
• #LI-AB1

Benefits

Additional Information

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Built on decades of expertise and execution, Marvell's custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you'll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, and networking applications. This position provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell. What You Can Expect In this onsite role, you will work with both local and global team members on the physical design of complex chips as well as the methodology to enable an efficient and robust design process. Work with design teams across various disciplines such as Digital/RTL/Analog to ensure design convergence and integration in a timely manner. Implement/support designs with multi-voltage designs through all aspects of implementation (place and route, static timing, physical verification) using industry standard EDA tools. Work with RTL design teams to drive assembly and design closure. Provide technical direction, coaching, and mentoring to junior employees and colleagues when necessary to achieve successful project outcomes. Write scripts in Shell, Python, and TCL to extract data and achieve productivity enhancements through automation.

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